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[Qemu-ppc] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp |
Date: |
Wed, 23 Nov 2016 17:07:16 +0530 |
stxsd: Store VSX Scalar Dword
stxssp: Store VSX Scalar SP
Moreover, DQ-Form/DS-FORM instructions shares the same primary
opcode(0x3D). For DQ-FORM bits 29:31 are used, for DS-FORM bits 30:31
are used. Common routine to decode primary opcode(0x3D) -
ds-form/dq-form instructions is required.
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 34 ++++++++++++++++++++++++++++++++++
target-ppc/translate/fp-ops.inc.c | 1 -
target-ppc/translate/vsx-impl.inc.c | 21 +++++++++++++++++++++
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9114f85..a1bf74c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6076,6 +6076,38 @@ static void gen_dform39(DisasContext *ctx)
return gen_invalid(ctx);
}
+/* handles stfdp, stxsd, stxssp */
+static void gen_dform3D(DisasContext *ctx)
+{
+ if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
+ switch (ctx->opcode & 0x7) {
+ case 1: /* lxv */
+ break;
+ case 5: /* stxv */
+ break;
+ }
+ } else { /* DS-FORM */
+ switch (ctx->opcode & 0x3) {
+ case 0: /* stfdp */
+ if (ctx->insns_flags2 & PPC2_ISA205) {
+ return gen_stfdp(ctx);
+ }
+ break;
+ case 2: /* stxsd */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_stxsd(ctx);
+ }
+ break;
+ case 3: /* stxssp */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_stxssp(ctx);
+ }
+ break;
+ }
+ }
+ return gen_invalid(ctx);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -6150,6 +6182,8 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
+/* handles stfdp, stxsd, stxssp */
+GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
diff --git a/target-ppc/translate/fp-ops.inc.c
b/target-ppc/translate/fp-ops.inc.c
index 3127fa0..3c6d05a 100644
--- a/target-ppc/translate/fp-ops.inc.c
+++ b/target-ppc/translate/fp-ops.inc.c
@@ -87,7 +87,6 @@ GEN_STXF(name, stop, 0x17, op | 0x00, type)
GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
-GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 1d7cd23..8ee44cf 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -332,6 +332,27 @@ static void gen_stxvb16x(DisasContext *ctx)
tcg_temp_free(EA);
}
+#define VSX_STORE_SCALAR_DS(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_imm_index(ctx, EA, 0x03); \
+ gen_qemu_##operation(ctx, xth, EA); \
+ /* NOTE: cpu_vsrl is undefined */ \
+ tcg_temp_free(EA); \
+}
+
+VSX_LOAD_SCALAR_DS(stxsd, st64_i64)
+VSX_LOAD_SCALAR_DS(stxssp, st32fs)
+
#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.7.4
- [Qemu-ppc] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 01/10] target-ppc: Consolidate instruction decode helpers, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 02/10] target-ppc: rename CRF_* defines as CRF_*_BIT, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 04/10] target-ppc: Add xscmpexp[dp, qp] instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 03/10] target-ppc: Fix xscmpodp and xscmpudp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 06/10] target-ppc: implement lxsd and lxssp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v1 05/10] target-ppc: Add xscmpoqp and xscmpuqp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 08/10] target-ppc: implement lxv/lxvx and stxv/stxvx, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions, Nikunj A Dadhania, 2016/11/23
[Qemu-ppc] [PATCH v1 10/10] target-ppc: add vextu[bhw]rx instructions, Nikunj A Dadhania, 2016/11/23
Re: [Qemu-ppc] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8, David Gibson, 2016/11/23