[Qemu-ppc] Question about FR/FI flags

[joserz]

Hello!

I noticed that we're not setting FR and FI flags as specified by PowerISA for 
floating-point operations, those are in FPSCR register. My tests using Risu 
failed when comparing such register.

FR flag is usually set to indicate that an instruction incremented the fraction 
during rounding and FI indicates an inexact result during rounding. FI is 
closely related to XX (inexact exception) - page 125.

After searching the mailing list I didn't find any mention to those flags so 
I'm not sure if they were left behind because they aren't important or if it's 
a bug indeed. Does anybody know about it?

Thanks!

Ziviani