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Re: [Qemu-ppc] [PATCH 0/6] POWER9 TCG enablements - part15


From: David Gibson
Subject: Re: [Qemu-ppc] [PATCH 0/6] POWER9 TCG enablements - part15
Date: Fri, 10 Feb 2017 11:28:57 +1100
User-agent: Mutt/1.7.1 (2016-10-04)

On Thu, Feb 09, 2017 at 04:03:59PM +0530, Nikunj A Dadhania wrote:
> This series contains 6 new instructions for POWER9 ISA3.0

I've merged 1-4, 5 has comments.

> 
> Nikunj A Dadhania (6):
>   target-ppc: generate exception for copy/paste
>   target-ppc: add slbieg instruction
>   target-ppc: add slbsync implementation
>   target-ppc: add wait instruction
>   target-ppc: support for 32-bit carry and overflow
>   target-ppc: add mcrxrx instruction
> 
>  target/ppc/cpu.h        | 26 ++++++++++++++++++
>  target/ppc/helper.h     |  1 +
>  target/ppc/mmu-hash64.c | 16 +++++++++--
>  target/ppc/translate.c  | 72 
> +++++++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 113 insertions(+), 2 deletions(-)
> 

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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