[Qemu-ppc] [PATCH 18/25] spapr: allocate IRQ numbers for the XIVE interrupt mode

[Cédric Le Goater]

The IRQ numbers for the IPIs are allocated at the bottom of the IRQ
number space to preserve compatibility with XICS which only uses IRQ
numbers above 4096.

Also make sure that the allocated IRQ numbers are kept in sync between
XICS and XIVE.

Signed-off-by: Cédric Le Goater <address@hidden>
---
 hw/ppc/spapr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0e0107c8272c..ca4e72187f60 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2392,6 +2392,11 @@ static void ppc_spapr_init(MachineState *machine)
          * use the range below XICS_IRQ_BASE, which is unused by XICS. */
         spapr->xive = spapr_xive_create(spapr, XICS_IRQ_BASE + XICS_IRQS_SPAPR,
                                         &error_fatal);
+
+        /* Allocate the first IRQ numbers for the XIVE IPIs */
+        for (i = 0; i < xics_max_server_number(); ++i) {
+            spapr_xive_irq_set(spapr->xive, i, false);
+        }
     }
 
     /* Set up containers for ibm,client-architecture-support negotiated options
@@ -3631,6 +3636,7 @@ static int ics_find_free_block(ICSState *ics, int num, 
int alignnum)
 static void spapr_irq_set(sPAPRMachineState *spapr, int irq, bool lsi)
 {
     ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi);
+    spapr_xive_irq_set(spapr->xive, irq, lsi);
 }
 
 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
@@ -3721,6 +3727,7 @@ void spapr_irq_free(sPAPRMachineState *spapr, int irq, 
int num)
             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
         }
     }
+    spapr_xive_irq_unset(spapr->xive, irq);
 }
 
 qemu_irq spapr_irq_get_qirq(sPAPRMachineState *spapr, int irq)
-- 
2.13.6