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[Qemu-ppc] [PULL 22/22] target-ppc: Fix booke206 tlbwe TLB instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 22/22] target-ppc: Fix booke206 tlbwe TLB instruction |
Date: |
Wed, 17 Jan 2018 13:25:25 +1100 |
From: Luc MICHEL <address@hidden>
When overwritting a valid TLB entry with a new one, the previous page
were not flushed in QEMU TLB, leading to incoherent mapping. This commit
fixes this.
Signed-off-by: Luc MICHEL <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/mmu_helper.c | 32 +++++++++++++++++++++++++++-----
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 2a1f9902c9..298c15e961 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2570,6 +2570,17 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t
pidn, target_ulong pid)
tlb_flush(CPU(cpu));
}
+static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
+ tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
+ } else {
+ tlb_flush(CPU(cpu));
+ }
+}
+
void helper_booke206_tlbwe(CPUPPCState *env)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
@@ -2628,6 +2639,21 @@ void helper_booke206_tlbwe(CPUPPCState *env)
if (msr_gs) {
cpu_abort(CPU(cpu), "missing HV implementation\n");
}
+
+ if (tlb->mas1 & MAS1_VALID) {
+ /* Invalidate the page in QEMU TLB if it was a valid entry.
+ *
+ * In "PowerPC e500 Core Family Reference Manual, Rev. 1",
+ * Section "12.4.2 TLB Write Entry (tlbwe) Instruction":
+ * (https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf)
+ *
+ * "Note that when an L2 TLB entry is written, it may be displacing an
+ * already valid entry in the same L2 TLB location (a victim). If a
+ * valid L1 TLB entry corresponds to the L2 MMU victim entry, that L1
+ * TLB entry is automatically invalidated." */
+ flush_page(env, tlb);
+ }
+
tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |
env->spr[SPR_BOOKE_MAS3];
tlb->mas1 = env->spr[SPR_BOOKE_MAS1];
@@ -2663,11 +2689,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
tlb->mas1 &= ~MAS1_IPROT;
}
- if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
- tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
- } else {
- tlb_flush(CPU(cpu));
- }
+ flush_page(env, tlb);
}
static inline void booke206_tlb_to_mas(CPUPPCState *env, ppcmas_tlb_t *tlb)
--
2.14.3
- [Qemu-ppc] [PULL 21/22] target/ppc: add support for POWER9 HILE, (continued)
- [Qemu-ppc] [PULL 21/22] target/ppc: add support for POWER9 HILE, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 09/22] spapr: Remove unnecessary 'options' field from sPAPRCapabilityInfo, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 07/22] spapr: Handle Decimal Floating Point (DFP) as an optional capability, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 06/22] spapr: Handle VMX/VSX presence as an spapr capability flag, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 03/22] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 18/22] ppc/pnv: introduce pnv*_is_power9() helpers, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 17/22] ppc/pnv: change core mask for POWER9, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 13/22] spapr: Adjust default VSMT value for better migration compatibility, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 12/22] spapr: Allow some cases where we can't set VSMT mode in the kernel, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 02/22] spapr: Capabilities infrastructure, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 22/22] target-ppc: Fix booke206 tlbwe TLB instruction,
David Gibson <=
- [Qemu-ppc] [PULL 19/22] ppc/pnv: fix XSCOM core addressing on POWER9, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 01/22] target/ppc: Yet another fix for KVM-HV HPTE accessors, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 10/22] ppc: Change Power9 compat table to support at most 8 threads/core, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 05/22] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 11/22] target/ppc: Clarify compat mode max_threads value, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 20/22] ppc/pnv: change initrd address, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 16/22] ppc/pnv: use POWER9 DD2 processor, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 15/22] tests/boot-serial-test: fix powernv support, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 08/22] hw/ppc/spapr_caps: Rework spapr_caps to use uint8 internal representation, David Gibson, 2018/01/16
- Re: [Qemu-ppc] [PULL 00/22] ppc-for-2.12 queue 20180117, Peter Maydell, 2018/01/18