Re: [Qemu-ppc] [OpenBIOS] Apple's BootX

[James Lyons]

On 01/30/2018 10:47 AM, Jd Lyons wrote:
> > On Jan 30, 2018, at 9:10 AM, BALATON Zoltan <address@hidden> wrote:
> >
> > On Mon, 29 Jan 2018, Jd Lyons via OpenBIOS wrote:
> > > Ok, with a little help for Paul at the kvm-ppc mailing list, it seems the issue 
> > > maybe that the BootX or more likely mach_kernel it trying to write something to 
> > > or probe for an L3 cache.
> > With kvm could be but on TCG it doesn't seem that way. Enabling some SPR debug 
> > options in target/ppc/translate_init.c I see this (with qemu git HEAD without 
> > other patches):
> >
> > $ ppc-softmmu/qemu-system-ppc -cpu G4 -d int
> > Write SPR 272 110 <= 07e00000
> > Read SPR 287 11f => 000c0209
> > Read SPR 25 019 => 07e00000
> > Read SPR 25 019 => 07e00000
> > Read SPR 287 11f => 000c0209
> > Raise exception at fff08978 => 00000003 (40000000)
> > Write SPR 273 111 <= 07df7ff0
> > Write SPR 274 112 <= 20000004
> > Read SPR 272 110 => 07e00000
> > Read SPR 273 111 => 07df7ff0
> > Read SPR 274 112 => 20000004
> > Read SPR 26 01a => fff08978
> > Read SPR 27 01b => 40000030
> >
> > $ ppc-softmmu/qemu-system-ppc -cpu 7447a -d int
> > Write SPR 272 110 <= 07e00000
> > Read SPR 287 11f => 80030102
> > Read SPR 25 019 => 07e00000
> > Read SPR 25 019 => 07e00000
> > Read SPR 287 11f => 80030102
> > Raise exception at fff08978 => 0000004e (00)
> >
> > So OpenBIOS gets unexpected exception very early right after reading the PVR so 
> > maybe it's a problem in OpenBIOS before it gets to what you're describing. Is 
> > this already fixed?
> >
> > Regards,
> > BALATON Zoltan
> >
> > --
> > OpenBIOS                 http://openbios.org/
> > Mailinglist:  http://lists.openbios.org/mailman/listinfo
> > Free your System - May the Forth be with you
> It looks like in TCG mode that it tries to read these invalid spr’s
>
> 1018
> 1011
> 1016
> 1012
>
> This doesn’t cause a halt, as the kernel boots.

I went ahead an added these spr's to the 74xx cpu, hoping that adding 
the L3CR would allow me to boot in KVM mode with -cpu host or -cpu 
7447a_v1.5, but It didn't now the kernel hangs and I get the dmesg:

KVM: invalid SPR read: 1018

So I'm not doing it correctly or I'll have to do it in KVM and recompile 
the kernel for my host.

Here is the code I used for the L3CR, can anyone tell me a better way of 
doing it?


 /* L3CR */
    /* XXX : not implemented */
    spr_register(env, SPR_L3CR, "L3CR",
                 SPR_NOACCESS, SPR_NOACCESS,
                 &spr_read_generic, &spr_write_generic,
                 0x00000000);

In TCG( -cpu 7447a_v1.5 without enable-kvm ) mode I no longer get 
invalid spr reads between BootX( Call Kernel! ) and mach_kernel .
loading.

If I set the value of the register to 0x80000000 the guest mach_kernel 
tries to make a write there in TCG mode, and booting halts.

So, I'm guessing that mach_kernel expects the value here to be 
0x00000000, and if it isn't it tries to write something there.


In KVM mode the Kernel is unable to read the register. So I've got to 
figure some way around that. Or figure out why the kernel is trying to 
read this register for a CPU that doesn't support an L3 cache?

I don't know if this is an issue with Qemu, or the kernel reads this 
register when I boot native on the bare metal. Anyone know a way of 
getting a dump of register access on the bare metal?
>