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[Qemu-ppc] PPC440 bus frequencies and timers


From: BALATON Zoltan
Subject: [Qemu-ppc] PPC440 bus frequencies and timers
Date: Tue, 13 Mar 2018 13:35:48 +0100 (CET)
User-agent: Alpine 2.21 (BSF 202 2017-01-01)

Hello,

Anyone here with knowledge about PPC440 (especially as used in AMCC460EX SoC that the Sam460ex board is built on)? I see some problems related to timers and bus frequencies which are likely not emulated correctly but I don't know what's wrong or missing.

Problems I know about that may be related:

1. System time is going slower than expected in AROS (can be seen e.g. in Time Prefs). The seconds advance but much slower than they should. (AROS boot iso can be downloaded from http://aros.sourceforge.net/nightly1.php)

2. I had to set clock multipliers in SDR0_STRP0 register (that seems to have values for different internal buses of the SoC such as PLB and OPB) in qemu/hw/ppc/ppv440_uc.c:396 to 0 instead of a value more closely matching real hardware (although I'm not sure what real hardware has in this reg) because if I set the bits in comment for multipliers bus frequencies are printed correctly but this slows down U-Boot. A 0 value here works for U-Boot but makes the printed bus frequencies wrong. (I've also come across this u-boot patch https://lists.denx.de/pipermail/u-boot/2011-July/096848.html but haven't yet tried if it makes any difference.)

3. AmigaOS 4 boots very slowly which may be related as there seem to be a delay in IO operations (similar to U-Boot with non-0 value in STRP0) that could be because of a timer going slower than expected but I'm not sure without source what it really does. (There also seem to be graphics corruption issues with AmigaOS 4 but I could not identify yet if these are becuase of incomplete emulation of the SM502 chip or some other problem caused by delays due to timing (as writing SM502 registers seem to have a much longer delay than expected).

4. Linux kernel boots but hangs just before init should start. I'm not sure how to debug this to find out where's the problem so I'm not sure it's related but could be.

So there seems to be a problem with tb and other frequencies and timers relying on these but I don't know what's on real hardware and how exactly are these emulated in QEMU. Does anyone know more about these registers and how it works on real hardware and has any hints what could be the problem here? Any help is appreciated.

Regards,
BALATON Zoltan



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