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[Qemu-riscv] [PULL 09/11] MAINTAINERS: Remove Michael Clark as a RISC-V
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer |
Date: |
Wed, 13 Feb 2019 07:44:48 -0800 |
Michael is no longer employed by SiFive and does not want to continue
maintianing the RISC-V port.
Signed-off-by: Palmer Dabbelt <address@hidden>
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a2da141a928f..e170a4c73376 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -259,7 +259,6 @@ F: include/hw/ppc/
F: disas/ppc.c
RISC-V
-M: Michael Clark <address@hidden>
M: Palmer Dabbelt <address@hidden>
M: Alistair Francis <address@hidden>
M: Sagar Karandikar <address@hidden>
--
2.18.1
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 02/11] RISC-V: Mark mstatus.fs dirty, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 01/11] RISC-V: Split out mstatus_fs from tb_flags, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 04/11] RISC-V: Use riscv prefix consistently on cpu helpers, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 05/11] RISC-V: Add priv_ver to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 11/11] riscv: Ensure the kernel start address is correctly cast, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 08/11] RISC-V: Add misa runtime write support, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 10/11] target/riscv: fix counter-enable checks in ctr(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 03/11] RISC-V: Implement mstatus.TSR/TW/TVM, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 06/11] RISC-V: Add misa to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 07/11] RISC-V: Add misa.MAFD checks to translate, Palmer Dabbelt, 2019/02/13
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1, Peter Maydell, 2019/02/14