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[Qemu-riscv] [PATCH v8 28/34] target/riscv: Remove gen_system()
From: |
Bastian Koppelmann |
Subject: |
[Qemu-riscv] [PATCH v8 28/34] target/riscv: Remove gen_system() |
Date: |
Fri, 22 Feb 2019 15:10:18 +0100 |
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/translate.c | 34 ----------------------------------
1 file changed, 34 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index dedf4189d5..92be090bc7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -473,33 +473,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
-
static void decode_RV32_64C0(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -680,7 +653,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
static void decode_RV32_64G(DisasContext *ctx)
{
- int rs1, rd;
uint32_t op;
/* We do not do misaligned address check here: the address should never be
@@ -689,14 +661,8 @@ static void decode_RV32_64G(DisasContext *ctx)
* perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rd = GET_RD(ctx->opcode);
switch (op) {
- case OPC_RISC_SYSTEM:
- gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
- break;
default:
gen_exception_illegal(ctx);
break;
--
2.20.1
- [Qemu-riscv] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load(), (continued)
- [Qemu-riscv] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 27/34] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 29/34] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 19/34] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 06/34] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 12/34] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 28/34] target/riscv: Remove gen_system(),
Bastian Koppelmann <=
- [Qemu-riscv] [PATCH v8 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 13/34] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 30/34] target/riscv: Convert @cs_2 insns to share translation functions, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22