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[Qemu-stable] [PATCH 17/40] target-arm: Share all common TCG temporaries
From: |
Michael Roth |
Subject: |
[Qemu-stable] [PATCH 17/40] target-arm: Share all common TCG temporaries |
Date: |
Wed, 21 Oct 2015 12:51:47 -0500 |
From: Richard Henderson <address@hidden>
This is a bug fix for aarch64. At present, we have branches using
the 32-bit (translate.c) versions of cpu_[NZCV]F, but we set the flags
using the 64-bit (translate-a64.c) versions of cpu_[NZCV]F. From
the view of the TCG code generator, these are unrelated variables.
The bug is hard to see because we currently only read these variables
from branches, and upon reaching a branch TCG will first spill live
variables and then reload the arguments of the branch. Since the
32-bit versions were never live until reaching the branch, we'd re-read
the data that had just been spilled from the 64-bit versions.
There is currently no such problem with the cpu_exclusive_* variables,
but there's no point in tempting fate.
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
(cherry picked from commit 78bcaa3e37afbd0c5316634f917c13487384b6ca)
Signed-off-by: Michael Roth <address@hidden>
---
target-arm/translate-a64.c | 22 ----------------------
target-arm/translate.c | 10 +++++-----
target-arm/translate.h | 8 ++++++++
3 files changed, 13 insertions(+), 27 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 689f2be..0f923d3 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -39,16 +39,9 @@
static TCGv_i64 cpu_X[32];
static TCGv_i64 cpu_pc;
-static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
/* Load/store exclusive handling */
-static TCGv_i64 cpu_exclusive_addr;
-static TCGv_i64 cpu_exclusive_val;
static TCGv_i64 cpu_exclusive_high;
-#ifdef CONFIG_USER_ONLY
-static TCGv_i64 cpu_exclusive_test;
-static TCGv_i32 cpu_exclusive_info;
-#endif
static const char *regnames[] = {
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
@@ -104,23 +97,8 @@ void a64_translate_init(void)
regnames[i]);
}
- cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF),
"NF");
- cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF),
"ZF");
- cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF),
"CF");
- cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF),
"VF");
-
- cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
- cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_val), "exclusive_val");
cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_high), "exclusive_high");
-#ifdef CONFIG_USER_ONLY
- cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_test), "exclusive_test");
- cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUARMState, exclusive_info), "exclusive_info");
-#endif
}
static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 69ac18c..4385322 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -64,12 +64,12 @@ TCGv_ptr cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];
-static TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
-static TCGv_i64 cpu_exclusive_addr;
-static TCGv_i64 cpu_exclusive_val;
+TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
+TCGv_i64 cpu_exclusive_addr;
+TCGv_i64 cpu_exclusive_val;
#ifdef CONFIG_USER_ONLY
-static TCGv_i64 cpu_exclusive_test;
-static TCGv_i32 cpu_exclusive_info;
+TCGv_i64 cpu_exclusive_test;
+TCGv_i32 cpu_exclusive_info;
#endif
/* FIXME: These should be removed. */
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 9ab978f..679bdbc 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -62,7 +62,15 @@ typedef struct DisasContext {
TCGv_i64 tmp_a64[TMP_A64_MAX];
} DisasContext;
+/* Share the TCG temporaries common between 32 and 64 bit modes. */
extern TCGv_ptr cpu_env;
+extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
+extern TCGv_i64 cpu_exclusive_addr;
+extern TCGv_i64 cpu_exclusive_val;
+#ifdef CONFIG_USER_ONLY
+extern TCGv_i64 cpu_exclusive_test;
+extern TCGv_i32 cpu_exclusive_info;
+#endif
static inline int arm_dc_feature(DisasContext *dc, int feature)
{
--
1.9.1
- [Qemu-stable] [PATCH 00/40] Patch Round-up for stable 2.4.1, freeze on 2015-10-29, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 11/40] PPC: E500: Update u-boot to commit 79c884d7e4, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 12/40] s390x/css: start with cleared cstat/dstat, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 13/40] rtl8139: Fix receive buffer overflow check, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 15/40] cpus.c: qemu_mutex_lock_iothread fix race condition at cpu thread init, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 14/40] rtl8139: Do not consume the packet during overflow in standard mode., Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 17/40] target-arm: Share all common TCG temporaries,
Michael Roth <=
- [Qemu-stable] [PATCH 16/40] virtio dataplane: adapt dataplane for virtio Version 1, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 18/40] qcow2: Make size_to_clusters() return uint64_t, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 01/40] scsi-disk: Fix assertion failure on WRITE SAME, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 23/40] slirp: Fix non blocking connect for w32, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 24/40] ide: unify io_buffer_offset increments, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 22/40] nbd: release exp->blk after all clients are closed, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 19/40] ide: fix ATAPI command permissions, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 20/40] gtk: use setlocale() for LC_MESSAGES only, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 21/40] spapr_pci: fix device tree props for MSI/MSI-X, Michael Roth, 2015/10/21
- [Qemu-stable] [PATCH 25/40] qom: Do not reuse errp after a possible error, Michael Roth, 2015/10/21