error in compiling structural style of modeling?

[anand franklin]

Hello all,
 I am new to vhdl programme. I am getting error in
structural style of modeling, when i compile. i have
listed the error below after the code. Can any body
give light to it. i am using CYPRESS wrap package.
****************************************
--HALF ADDER VHDL PROGRAMME

library ieee;
use ieee.std_logic_1164.all;
entity HALF_ADDER is
        port(A,B:in BIT;SUM,CARRY:out BIT);
end HALF_ADDER;

architecture HA_STRUCTURE of HALF_ADDER is
        component XOR2
                port(X,Y:in BIT;Z: out BIT);
        end component;
        component AND2
                port(L,M:in BIT;N: out BIT);
        end component;
begin
        X1:XOR2 port map (A,B,SUM);
        A1:AND2 port map (A,B,CARRY);
end HA_STRUCTURE;
****************************************

***************Error*************************
halfadder.vhd (line 17, col 1):  (E441) Component
formal 'x' has no match in 'xor2' port list.
halfadder.vhd (line 17, col 1):  (E441) Component
formal 'y' has no match in 'xor2' port list.
halfadder.vhd (line 17, col 1):  (E441) Component
formal 'z' has no match in 'xor2' port list.
halfadder.vhd (line 17, col 1):  (E456) Entity formal
'a' is missing from COMPONENT 'xor2'.
halfadder.vhd (line 17, col 1):  (E456) Entity formal
'b' is missing from COMPONENT 'xor2'.
halfadder.vhd (line 17, col 1):  (E456) Entity formal
'q' is missing from COMPONENT 'xor2'.


help topics explains the error this way,
**********Help for E441
E441    :Component formal '%s' has no match in ‘%s’.

Check for an invalid port map or a typo during a
component instantiation.E441    :Component formal '%s'
has no match in ‘%s’.

Check for an invalid port map or a typo during a
component instantiation.


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