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qemu-riscv (date)
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Last Modified: Thu Jan 31 2019 18:04:43 -0500
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January 31, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
18:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
17:47
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:39
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:37
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:35
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:31
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:27
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
16:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
15:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
15:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
14:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
13:52
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
no-reply
,
13:22
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
no-reply
,
13:19
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
13:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree
,
no-reply
,
12:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
no-reply
,
12:50
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Peter Maydell
,
04:52
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Thomas Huth
,
01:40
January 30, 2019
[Qemu-riscv] [PATCH] RISC-V: Fix pmpcfg register indexing
,
Luke Nelson
,
17:20
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Palmer Dabbelt
,
14:01
[Qemu-riscv] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write
,
Fabien Chouteau
,
13:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
13:47
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Eric Blake
,
12:45
[Qemu-riscv] [PULL 07/10] RISC-V: Add misa.MAFD checks to translate
,
Palmer Dabbelt
,
12:37
[Qemu-riscv] [PULL 04/10] RISC-V: Use riscv prefix consistently on cpu helpers
,
Palmer Dabbelt
,
12:37
[Qemu-riscv] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Palmer Dabbelt
,
12:37
[Qemu-riscv] [PULL 02/10] RISC-V: Mark mstatus.fs dirty
,
Palmer Dabbelt
,
12:37
[Qemu-riscv] [PULL 05/10] RISC-V: Add priv_ver to DisasContext
,
Palmer Dabbelt
,
12:36
[Qemu-riscv] [PULL 09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
,
Palmer Dabbelt
,
12:36
[Qemu-riscv] [PULL 08/10] RISC-V: Add misa runtime write support
,
Palmer Dabbelt
,
12:36
[Qemu-riscv] [PULL 03/10] RISC-V: Implement mstatus.TSR/TW/TVM
,
Palmer Dabbelt
,
12:36
[Qemu-riscv] [PULL 10/10] target/riscv: fix counter-enable checks in ctr()
,
Palmer Dabbelt
,
12:36
[Qemu-riscv] [PULL 06/10] RISC-V: Add misa to DisasContext
,
Palmer Dabbelt
,
12:36
[Qemu-riscv] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags
,
Palmer Dabbelt
,
12:36
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
04:08
January 29, 2019
[Qemu-riscv] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Jim Wilson
,
21:57
[Qemu-riscv] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs.
,
Jim Wilson
,
21:57
[Qemu-riscv] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros.
,
Jim Wilson
,
21:56
[Qemu-riscv] [PATCH 2/5 v3] RISC-V: Add 64-bit gdb xml files.
,
Jim Wilson
,
21:55
[Qemu-riscv] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files.
,
Jim Wilson
,
21:54
[Qemu-riscv] [PATCH 0/5 v3] RISC-V: Add gdb xml files and gdbstub support.
,
Jim Wilson
,
21:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
,
Palmer Dabbelt
,
18:21
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Alistair Francis
,
16:14
Re: [Qemu-riscv] [PATCH] target/riscv: fix counter-enable checks in ctr()
,
Palmer Dabbelt
,
14:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
14:23
January 28, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
,
Jim Wilson
,
22:14
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
,
Jim Wilson
,
22:14
January 26, 2019
[Qemu-riscv] [PATCH] target/riscv: fix counter-enable checks in ctr()
,
Xi Wang
,
21:14
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
03:51
January 25, 2019
Re: [Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
18:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
,
Philippe Mathieu-Daudé
,
18:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G()
,
Alistair
,
17:30
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith
,
Alistair
,
17:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load()
,
Alistair
,
17:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Alistair
,
17:27
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store()
,
Alistair
,
17:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch()
,
Alistair
,
17:23
[Qemu-riscv] [PATCH] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
,
Palmer Dabbelt
,
17:21
January 24, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
,
Palmer Dabbelt
,
19:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3
,
Palmer Dabbelt
,
19:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 8/8] RISC-V: Add misa runtime write support
,
Palmer Dabbelt
,
19:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
,
Alistair Francis
,
19:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 1/1] riscv: Ensure the kernel start address is correctly cast
,
Philippe Mathieu-Daudé
,
17:00
[Qemu-riscv] [PATCH v3 1/1] riscv: Ensure the kernel start address is correctly cast
,
Alistair Francis
,
12:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 1/1] riscv: Ensure the kernel start address is correctly cast
,
Alistair Francis
,
12:37
Re: [Qemu-riscv] [PULL] RISC-V Updates for 3.2, Part 2
,
Peter Maydell
,
05:21
January 23, 2019
Re: [Qemu-riscv] [PULL] RISC-V Updates for 3.2, Part 2
,
Palmer Dabbelt
,
21:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 1/1] riscv: Ensure the kernel start address is correctly cast
,
Palmer Dabbelt
,
21:00
Re: [Qemu-riscv] [Qemu-devel] [RFC PATCH v4 14/44] hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards
,
Alistair Francis
,
17:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Alistair Francis
,
16:22
Re: [Qemu-riscv] [Qemu-devel] [RFC PATCH v4 14/44] hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards
,
Thomas Huth
,
13:16
[Qemu-riscv] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch()
,
Bastian Koppelmann
,
04:44
[Qemu-riscv] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Bastian Koppelmann
,
04:44
[Qemu-riscv] [PATCH v6 20/35] target/riscv: Remove gen_jalr()
,
Bastian Koppelmann
,
04:44
[Qemu-riscv] [PATCH v6 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Bastian Koppelmann
,
04:44
[Qemu-riscv] [PATCH v6 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
04:44
[Qemu-riscv] [PATCH v6 16/35] target/riscv: Convert RV priv insns to decodetree
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load()
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 29/35] target/riscv: Remove gen_system()
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store()
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G()
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Bastian Koppelmann
,
04:43
[Qemu-riscv] [PATCH v6 12/35] target/riscv: Convert RV32F insns to decodetree
,
Bastian Koppelmann
,
04:27
[Qemu-riscv] [PATCH v6 15/35] target/riscv: Convert RV64D insns to decodetree
,
Bastian Koppelmann
,
04:27
[Qemu-riscv] [PATCH v6 14/35] target/riscv: Convert RV32D insns to decodetree
,
Bastian Koppelmann
,
04:27
[Qemu-riscv] [PATCH v6 13/35] target/riscv: Convert RV64F insns to decodetree
,
Bastian Koppelmann
,
04:27
[Qemu-riscv] [PATCH v6 11/35] target/riscv: Convert RV64A insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 08/35] target/riscv: Convert RVXI csr insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 10/35] target/riscv: Convert RV32A insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 09/35] target/riscv: Convert RVXM insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 04/35] target/riscv: Convert RV32I load/store insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 05/35] target/riscv: Convert RV64I load/store insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree
,
Bastian Koppelmann
,
04:26
[Qemu-riscv] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Bastian Koppelmann
,
04:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
04:15
January 22, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree
,
Alistair Francis
,
20:01
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree
,
Alistair Francis
,
19:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree
,
Alistair Francis
,
19:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree
,
Alistair Francis
,
19:08
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree
,
Alistair Francis
,
19:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree
,
Alistair Francis
,
18:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree
,
Alistair Francis
,
18:47
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree
,
Alistair Francis
,
18:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files.
,
Alistair Francis
,
16:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
,
Alistair Francis
,
16:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
,
Alistair Francis
,
16:52
Re: [Qemu-riscv] [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.
,
Alistair Francis
,
16:47
Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
,
Alistair Francis
,
16:46
Re: [Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Richard Henderson
,
16:39
Re: [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Richard Henderson
,
16:36
Re: [Qemu-riscv] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Richard Henderson
,
16:36
[Qemu-riscv] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 05/35] target/riscv: Convert RV64I load/store insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 09/35] target/riscv: Convert RVXM insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 20/35] target/riscv: Remove gen_jalr()
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 08/35] target/riscv: Convert RVXI csr insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 11/35] target/riscv: Convert RV64A insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store()
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load()
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch()
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 29/35] target/riscv: Remove gen_system()
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G()
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith
,
Bastian Koppelmann
,
04:38
[Qemu-riscv] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Bastian Koppelmann
,
04:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
04:01
January 21, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Richard Henderson
,
18:22
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
04:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
04:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree
,
Bastian Koppelmann
,
04:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Bastian Koppelmann
,
04:05
January 19, 2019
Re: [Qemu-riscv] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_arith
,
Richard Henderson
,
20:48
Re: [Qemu-riscv] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Richard Henderson
,
20:43
Re: [Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Richard Henderson
,
20:24
Re: [Qemu-riscv] [PATCH v4 16/35] target/riscv: Convert RV priv insns to decodetree
,
Richard Henderson
,
16:56
Re: [Qemu-riscv] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree
,
Richard Henderson
,
16:51
Re: [Qemu-riscv] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Richard Henderson
,
16:29
Re: [Qemu-riscv] [PATCH v4 04/35] target/riscv: Convert RV32I load/store insns to decodetree
,
Richard Henderson
,
16:21
January 18, 2019
[Qemu-riscv] [PATCH v4 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 27/35] target/riscv: Remove manual decoding of RV32/64M insn
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 29/35] target/riscv: Remove gen_system()
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 09/35] target/riscv: Convert RVXM insns to decodetree
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 14/35] target/riscv: Convert RV32D insns to decodetree
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch()
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G()
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 31/35] target/riscv: Convert @cs_2 insns to share translation functions<Paste>
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 10/35] target/riscv: Convert RV32A insns to decodetree
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 20/35] target/riscv: Remove gen_jalr()
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 22/35] target/riscv: Remove manual decoding from gen_load()
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_arith
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 23/35] target/riscv: Remove manual decoding from gen_store()
,
Bastian Koppelmann
,
08:16
[Qemu-riscv] [PATCH v4 16/35] target/riscv: Convert RV priv insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 11/35] target/riscv: Convert RV64A insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 15/35] target/riscv: Convert RV64D insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 13/35] target/riscv: Convert RV64F insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 05/35] target/riscv: Convert RV64I load/store insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 04/35] target/riscv: Convert RV32I load/store insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 03/35] target/riscv: Convert RVXI branch insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 08/35] target/riscv: Convert RVXI csr insns to decodetree
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Bastian Koppelmann
,
08:15
[Qemu-riscv] [PATCH v4 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
08:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
07:00
January 16, 2019
Re: [Qemu-riscv] [Qemu-devel] [RFC PATCH v2 13/37] hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards
,
Thomas Huth
,
09:02
January 15, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
,
Alistair Francis
,
17:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate
,
Richard Henderson
,
17:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
,
Richard Henderson
,
17:24
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
,
Richard Henderson
,
17:21
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 1/1] riscv: Ensure the kernel start address is correctly cast
,
Alistair Francis
,
16:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
,
Philippe Mathieu-Daudé
,
14:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
,
Alistair Francis
,
12:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
,
Philippe Mathieu-Daudé
,
12:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
,
Philippe Mathieu-Daudé
,
05:50
January 14, 2019
[Qemu-riscv] [PATCH v1 8/8] RISC-V: Add misa runtime write support
,
Alistair Francis
,
18:59
[Qemu-riscv] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate
,
Alistair Francis
,
18:59
[Qemu-riscv] [PATCH v1 6/8] RISC-V: Add misa to DisasContext
,
Alistair Francis
,
18:59
[Qemu-riscv] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
,
Alistair Francis
,
18:59
[Qemu-riscv] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
,
Alistair Francis
,
18:58
[Qemu-riscv] [PATCH v1 3/8] RISC-V: Implement mstatus.TSR/TW/TVM
,
Alistair Francis
,
18:58
[Qemu-riscv] [PATCH v1 2/8] RISC-V: Mark mstatus.fs dirty
,
Alistair Francis
,
18:58
[Qemu-riscv] [PATCH v1 1/8] RISC-V: Split out mstatus_fs from tb_flags
,
Alistair Francis
,
18:57
[Qemu-riscv] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3
,
Alistair Francis
,
18:57
Re: [Qemu-riscv] [PULL] RISC-V Updates for 3.2, Part 2
,
Peter Maydell
,
07:40
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 1/1] riscv: Ensure the kernel start address is correctly cast
,
Philippe Mathieu-Daudé
,
05:59
January 11, 2019
[Qemu-riscv] [PATCH v2 1/1] riscv: Ensure the kernel start address is correctly cast
,
Alistair Francis
,
20:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Richard Henderson
,
16:00
[Qemu-riscv] [PULL 1/4] RISC-V: Implement modular CSR helper interface
,
Palmer Dabbelt
,
13:06
[Qemu-riscv] [PULL 3/4] RISC-V: Implement existential predicates for CSRs
,
Palmer Dabbelt
,
13:06
[Qemu-riscv] [PULL 2/4] RISC-V: Implement atomic mip/sip CSR updates
,
Palmer Dabbelt
,
13:06
[Qemu-riscv] [PULL 4/4] default-configs: Enable USB support for RISC-V machines
,
Palmer Dabbelt
,
13:06
[Qemu-riscv] [PULL] RISC-V Updates for 3.2, Part 2
,
Palmer Dabbelt
,
13:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
08:10
January 10, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] default-configs: Enable USB support for RISC-V machines
,
Alistair Francis
,
17:28
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] default-configs: Enable USB support for RISC-V machines
,
Palmer Dabbelt
,
11:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] default-configs: Enable USB support for RISC-V machines
,
Thomas Huth
,
03:33
January 09, 2019
[Qemu-riscv] [PATCH v1 1/1] default-configs: Enable USB support for RISC-V machines
,
Alistair Francis
,
19:01
Re: [Qemu-riscv] [Qemu-devel] Wiki Account Creation [Was Re: [PULL] RISC-V Changes for 3.2, Part 1]
,
Palmer Dabbelt
,
14:37
January 08, 2019
Re: [Qemu-riscv] [Qemu-devel] Wiki Account Creation [Was Re: [PULL] RISC-V Changes for 3.2, Part 1]
,
Max Filippov
,
16:11
[Qemu-riscv] Wiki Account Creation [Was Re: [PULL] RISC-V Changes for 3.2, Part 1]
,
Palmer Dabbelt
,
14:37
January 06, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 0/3] Upstream more RISC-V fork patches
,
Richard Henderson
,
04:12
January 04, 2019
[Qemu-riscv] [PATCH v1 3/3] RISC-V: Implement existential predicates for CSRs
,
Alistair Francis
,
18:24
[Qemu-riscv] [PATCH v1 1/3] RISC-V: Implement modular CSR helper interface
,
Alistair Francis
,
18:24
[Qemu-riscv] [PATCH v1 2/3] RISC-V: Implement atomic mip/sip CSR updates
,
Alistair Francis
,
18:24
[Qemu-riscv] [PATCH v1 0/3] Upstream more RISC-V fork patches
,
Alistair Francis
,
18:23
January 03, 2019
Re: [Qemu-riscv] [PULL] RISC-V Changes for 3.2, Part 1
,
Peter Maydell
,
11:46
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