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qemu-riscv (date)
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Last Modified: Tue Jun 30 2020 20:19:44 -0400
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June 30, 2020
Re: [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT
,
LIU Zhiwei
,
20:19
Re: [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode
,
LIU Zhiwei
,
20:17
Re: [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode
,
Richard Henderson
,
17:51
[PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode
,
Alistair Francis
,
16:21
[PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT
,
Alistair Francis
,
16:21
[PATCH v1 1/3] hw/char: Convert the Ibex UART to use the qdev Clock model
,
Alistair Francis
,
16:21
[PATCH v1 0/3] A few RISC-V fixes
,
Alistair Francis
,
16:21
Re: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits
,
LIU Zhiwei
,
11:38
Re: [PATCH 1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN
,
LIU Zhiwei
,
11:23
Re: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits
,
Richard Henderson
,
11:01
Re: [PATCH 1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN
,
Richard Henderson
,
10:56
[PATCH v3 18/26] riscv_hart: Fix riscv_harts_realize() error API violations
,
Markus Armbruster
,
05:04
[PATCH v3 17/26] riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
,
Markus Armbruster
,
05:04
Re: [PATCH 5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN
,
LIU Zhiwei
,
03:37
Re: [PATCH 5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN
,
Chih-Min Chao
,
03:31
Re: [PATCH 3/6] target/riscv: Check for LEGAL NaN-boxing
,
LIU Zhiwei
,
03:31
Re: [PATCH 3/6] target/riscv: Check for LEGAL NaN-boxing
,
Chih-Min Chao
,
03:21
June 29, 2020
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Bin Meng
,
21:04
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
14:50
[PATCH 1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN
,
LIU Zhiwei
,
09:07
[PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits
,
LIU Zhiwei
,
09:07
[PATCH 0/2] target/riscv: fixup atomic implementation
,
LIU Zhiwei
,
09:07
June 27, 2020
Re: [PATCH for 5.0 v1 1/2] riscv: Don't use stage-2 PTE lookup protection flags
,
Richard Henderson
,
18:48
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Bin Meng
,
06:04
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Bin Meng
,
05:55
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Alistair Francis
,
01:32
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
00:37
June 26, 2020
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Bin Meng
,
22:54
Re: [PATCH 0/6] target/riscv: NaN-boxing for multiple precison
,
no-reply
,
17:22
[PATCH 6/6] target/riscv: clean up fmv.w.x
,
LIU Zhiwei
,
17:11
[PATCH 5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN
,
LIU Zhiwei
,
17:09
[PATCH 4/6] target/riscv: check before allocating TCG temps
,
LIU Zhiwei
,
17:07
[PATCH 3/6] target/riscv: Check for LEGAL NaN-boxing
,
LIU Zhiwei
,
17:05
[PATCH 2/6] target/riscv: NaN-boxing compute, sign-injection and convert instructions.
,
LIU Zhiwei
,
17:03
[PATCH 1/6] target/riscv: move gen_nanbox_fpr to translate.c
,
LIU Zhiwei
,
17:01
[PATCH 0/6] target/riscv: NaN-boxing for multiple precison
,
LIU Zhiwei
,
16:59
Re: [PATCH v3 3/3] riscv: Add opensbi firmware dynamic support
,
Atish Patra
,
14:49
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
12:58
[PATCH] MAINTAINERS: Add an entry for OpenSBI firmware
,
Bin Meng
,
09:09
Re: [PATCH v3 3/3] riscv: Add opensbi firmware dynamic support
,
Bin Meng
,
08:17
Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Bin Meng
,
07:50
Re: [PATCH v3 1/3] riscv: Unify Qemu's reset vector code path
,
Bin Meng
,
06:25
RE: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
02:43
June 25, 2020
[PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
20:33
[PATCH v3 3/3] riscv: Add opensbi firmware dynamic support
,
Atish Patra
,
20:33
[PATCH v3 1/3] riscv: Unify Qemu's reset vector code path
,
Atish Patra
,
20:33
[PATCH v3 0/3] Add OpenSBI dynamic firmware support
,
Atish Patra
,
20:33
Re: [PATCH v2 1/3] riscv: Unify Qemu's reset vector code path
,
Atish Patra
,
16:09
Re: [PATCH v2 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Alistair Francis
,
16:04
Re: [PATCH v2 3/3] riscv: Add opensbi firmware dynamic support
,
Alistair Francis
,
16:00
Re: [PATCH v2 1/3] riscv: Unify Qemu's reset vector code path
,
Alistair Francis
,
15:50
Re: [PATCH for 5.0 v1 1/2] riscv: Don't use stage-2 PTE lookup protection flags
,
Alistair Francis
,
15:12
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Alistair Francis
,
14:59
[PATCH v2 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
14:38
[PATCH v2 1/3] riscv: Unify Qemu's reset vector code path
,
Atish Patra
,
14:37
[PATCH v2 3/3] riscv: Add opensbi firmware dynamic support
,
Atish Patra
,
14:37
[PATCH v2 0/3] Add OpenSBI dynamic firmware support
,
Atish Patra
,
14:37
Re: [PATCH v2 1/7] configure: Create symbolic links for pc-bios/*.elf files
,
Philippe Mathieu-Daudé
,
11:33
June 24, 2020
Re: [PATCH v2 1/7] configure: Create symbolic links for pc-bios/*.elf files
,
Alistair Francis
,
15:28
Re: [PATCH v11 00/61] target/riscv: support vector extension v0.7.1
,
Alistair Francis
,
09:54
[PATCH v2 17/25] riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
,
Markus Armbruster
,
04:38
[PATCH v2 18/25] riscv_hart: Fix riscv_harts_realize() error API violations
,
Markus Armbruster
,
04:37
June 23, 2020
Re: [PATCH v11 00/61] target/riscv: support vector extension v0.7.1
,
no-reply
,
20:11
[PATCH v11 61/61] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
20:02
[PATCH v11 60/61] target/riscv: vector compress instruction
,
LIU Zhiwei
,
20:00
[PATCH v11 59/61] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
19:58
[PATCH v11 58/61] target/riscv: vector slide instructions
,
LIU Zhiwei
,
19:56
[PATCH v11 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
19:54
[PATCH v11 56/61] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
19:52
[PATCH v11 55/61] target/riscv: integer extract instruction
,
LIU Zhiwei
,
19:50
[PATCH v11 54/61] target/riscv: vector element index instruction
,
LIU Zhiwei
,
19:48
[PATCH v11 53/61] target/riscv: vector iota instruction
,
LIU Zhiwei
,
19:46
[PATCH v11 52/61] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
19:44
[PATCH v11 51/61] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
19:42
[PATCH v11 50/61] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
19:40
[PATCH v11 49/61] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
19:38
[PATCH v11 48/61] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
19:36
[PATCH v11 47/61] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
19:34
[PATCH v11 46/61] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
19:32
[PATCH v11 45/61] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
19:30
[PATCH v11 44/61] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
19:28
[PATCH v11 43/61] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
19:26
[PATCH v11 42/61] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
19:24
[PATCH v11 41/61] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
19:22
[PATCH v11 40/61] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
19:20
[PATCH v11 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
19:18
[PATCH v11 38/61] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
19:16
[PATCH v11 37/61] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
19:14
[PATCH v11 36/61] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
19:12
[PATCH v11 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
19:10
[PATCH v11 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
19:08
[PATCH v11 33/61] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
19:06
[PATCH v11 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
19:04
[PATCH v11 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
19:02
[PATCH v11 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
19:00
[PATCH v11 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
18:58
[PATCH v11 28/61] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
18:56
[PATCH v11 27/61] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
18:54
[PATCH v11 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
18:52
[PATCH v11 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
18:50
[PATCH v11 24/61] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
18:48
[PATCH v11 23/61] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
18:46
[PATCH v11 22/61] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
18:44
[PATCH v11 21/61] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
18:42
[PATCH v11 20/61] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
18:40
[PATCH v11 19/61] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
18:38
[PATCH v11 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
18:36
[PATCH v11 17/61] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
18:34
[PATCH v11 16/61] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
18:32
[PATCH v11 15/61] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
18:30
[PATCH v11 14/61] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
18:28
[PATCH v11 13/61] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
18:26
[PATCH v11 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
18:24
[PATCH v11 11/61] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
18:22
[PATCH v11 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
18:20
[PATCH v11 09/61] target/riscv: add vector amo operations
,
LIU Zhiwei
,
18:18
[PATCH v11 08/61] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
18:16
[PATCH v11 07/61] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
18:14
[PATCH v11 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
18:12
[PATCH v11 05/61] target/riscv: add an internals.h header
,
LIU Zhiwei
,
18:10
[PATCH v11 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
18:08
[PATCH v11 03/61] target/riscv: support vector extension csr
,
LIU Zhiwei
,
18:06
[PATCH v11 02/61] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
18:04
[PATCH v11 01/61] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
18:02
[PATCH v11 00/61] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
18:00
Re: [PATCH v10 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
17:33
Re: [PATCH v10 06/61] target/riscv: add vector stride load and store instructions
,
Alistair Francis
,
13:01
Re: [Qemu-devel] [Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Alistair Francis
,
12:17
Re: [Qemu-devel] [Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Bin Meng
,
02:35
June 22, 2020
Re: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images
,
Alistair Francis
,
17:41
Re: [PATCH v2 2/7] roms/opensbi: Upgrade from v0.7 to v0.8
,
Alistair Francis
,
17:35
Re: [PATCH 18/22] riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
,
Alistair Francis
,
17:33
Re: [PATCH 19/22] riscv_hart: Fix riscv_harts_realize() error API violations
,
Alistair Francis
,
17:28
RE: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images
,
Anup Patel
,
08:34
Re: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images
,
Bin Meng
,
08:27
RE: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images
,
Anup Patel
,
08:20
Re: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images
,
Bin Meng
,
08:13
[PATCH 19/22] riscv_hart: Fix riscv_harts_realize() error API violations
,
Markus Armbruster
,
06:43
[PATCH 18/22] riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
,
Markus Armbruster
,
06:43
RE: [PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images
,
Anup Patel
,
06:09
[PATCH v2 6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform
,
Bin Meng
,
02:34
[PATCH v2 7/7] Makefile: Ship the generic platform bios images for RISC-V
,
Bin Meng
,
02:33
[PATCH v2 3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
,
Bin Meng
,
02:33
[PATCH v2 5/7] hw/riscv: spike: Change the default bios to use generic platform image
,
Bin Meng
,
02:33
[PATCH v2 4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
02:33
[PATCH v2 2/7] roms/opensbi: Upgrade from v0.7 to v0.8
,
Bin Meng
,
02:33
[PATCH v2 1/7] configure: Create symbolic links for pc-bios/*.elf files
,
Bin Meng
,
02:33
[PATCH v2 0/7] riscv: Switch to use generic platform of opensbi bios images
,
Bin Meng
,
02:33
June 20, 2020
[PATCH v10 61/61] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
02:40
[PATCH v10 60/61] target/riscv: vector compress instruction
,
LIU Zhiwei
,
02:38
[PATCH v10 59/61] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
02:36
[PATCH v10 58/61] target/riscv: vector slide instructions
,
LIU Zhiwei
,
02:34
[PATCH v10 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
02:32
[PATCH v10 56/61] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
02:29
[PATCH v10 55/61] target/riscv: integer extract instruction
,
LIU Zhiwei
,
02:27
[PATCH v10 54/61] target/riscv: vector element index instruction
,
LIU Zhiwei
,
02:25
[PATCH v10 53/61] target/riscv: vector iota instruction
,
LIU Zhiwei
,
02:23
[PATCH v10 52/61] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
02:21
[PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
02:19
[PATCH v10 50/61] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
02:18
[PATCH v10 49/61] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
02:15
[PATCH v10 48/61] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
02:13
[PATCH v10 47/61] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
02:11
[PATCH v10 46/61] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
02:09
[PATCH v10 45/61] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
02:07
[PATCH v10 44/61] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
02:05
[PATCH v10 43/61] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
02:03
[PATCH v10 42/61] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
02:01
[PATCH v10 41/61] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
01:59
[PATCH v10 40/61] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
01:57
[PATCH v10 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
01:55
[PATCH v10 38/61] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
01:53
[PATCH v10 37/61] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
01:51
[PATCH v10 36/61] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
01:49
[PATCH v10 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
01:47
[PATCH v10 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
01:45
[PATCH v10 33/61] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
01:43
[PATCH v10 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
01:41
[PATCH v10 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
01:39
[PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
01:37
[PATCH v10 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
01:35
[PATCH v10 28/61] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
01:33
[PATCH v10 27/61] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
01:31
[PATCH v10 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
01:29
[PATCH v10 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
01:27
[PATCH v10 24/61] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
01:25
[PATCH v10 23/61] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
01:23
[PATCH v10 22/61] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
01:21
[PATCH v10 21/61] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
01:19
[PATCH v10 20/61] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
01:17
[PATCH v10 19/61] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
01:15
[PATCH v10 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
01:13
[PATCH v10 17/61] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
01:11
[PATCH v10 16/61] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
01:09
[PATCH v10 15/61] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
01:07
[PATCH v10 14/61] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
01:05
[PATCH v10 13/61] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
01:03
[PATCH v10 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
01:01
[PATCH v10 11/61] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
00:59
[PATCH v10 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
00:57
[PATCH v10 09/61] target/riscv: add vector amo operations
,
LIU Zhiwei
,
00:55
[PATCH v10 08/61] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
00:53
[PATCH v10 07/61] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
00:51
[PATCH v10 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
00:49
[PATCH v10 05/61] target/riscv: add an internals.h header
,
LIU Zhiwei
,
00:47
[PATCH v10 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
00:45
[PATCH v10 03/61] target/riscv: support vector extension csr
,
LIU Zhiwei
,
00:43
[PATCH v10 02/61] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
00:41
[PATCH v10 01/61] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
00:39
[PATCH v10 00/61] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
00:37
[PATCH v10 37/61] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
00:10
[PATCH v10 36/61] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
00:08
[PATCH v10 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
00:06
[PATCH v10 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
00:04
[PATCH v10 33/61] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
00:02
[PATCH v10 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
00:00
June 19, 2020
[PATCH v10 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
23:58
[PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
23:56
[PATCH v10 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
23:54
[PATCH v10 28/61] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
23:52
[PATCH v10 27/61] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
23:50
[PATCH v10 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
23:48
[PATCH v10 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
23:46
[PATCH v10 24/61] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
23:44
[PATCH v10 23/61] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
23:42
[PATCH v10 22/61] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
23:40
[PATCH v10 21/61] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
23:38
[PATCH v10 20/61] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
23:36
[PATCH v10 19/61] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
23:34
[PATCH v10 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
23:32
[PATCH v10 17/61] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
23:30
[PATCH v10 16/61] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
23:28
[PATCH v10 15/61] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
23:26
[PATCH v10 14/61] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
23:24
[PATCH v10 13/61] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
23:22
[PATCH v10 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
23:20
[PATCH v10 11/61] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
23:18
[PATCH v10 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
23:16
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
23:14
[PATCH v10 09/61] target/riscv: add vector amo operations
,
LIU Zhiwei
,
23:14
[PATCH v10 08/61] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
23:12
[PATCH v10 07/61] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
23:10
[PATCH v10 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
23:08
[PATCH v10 05/61] target/riscv: add an internals.h header
,
LIU Zhiwei
,
23:06
[PATCH v10 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
23:04
[PATCH v10 03/61] target/riscv: support vector extension csr
,
LIU Zhiwei
,
23:02
[PATCH v10 02/61] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
23:00
[PATCH v10 01/61] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
22:57
[PATCH v10 00/61] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
22:56
Re: [PATCH v9 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
21:40
Re: [PATCH v9 57/61] target/riscv: floating-point scalar move instructions
,
Alistair Francis
,
21:15
Re: [PATCH v9 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
21:10
Re: [PATCH v9 57/61] target/riscv: floating-point scalar move instructions
,
Alistair Francis
,
20:54
Re: [PATCH] riscv: plic: Add a couple of mising sifive_plic_update calls
,
Alistair Francis
,
17:28
Re: [PATCH v2] riscv: plic: Honour source priorities
,
Alistair Francis
,
17:23
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Alistair Francis
,
17:15
Re: [PATCH 1/3] riscv: Unify Qemu's reset vector code path
,
Atish Patra
,
16:34
Re: [PATCH 1/3] riscv: Unify Qemu's reset vector code path
,
Alexander Richardson
,
12:37
Re: [PATCH 0/3] Add OpenSBI dynamic firmware support
,
Alexander Richardson
,
12:32
Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Alistair Francis
,
02:14
June 18, 2020
Re: [PATCH v1 2/2] sifive_e: Support the revB machine
,
Palmer Dabbelt
,
23:42
Re: [PATCH 1/3] riscv: Unify Qemu's reset vector code path
,
Atish Patra
,
21:56
Re: [PATCH 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
21:53
Re: [PATCH v1 2/2] sifive_e: Support the revB machine
,
Alistair Francis
,
19:27
Re: [PATCH v1 2/2] sifive_e: Support the revB machine
,
Palmer Dabbelt
,
18:43
[PATCH v2] riscv: plic: Honour source priorities
,
Jessica Clarke
,
17:34
[PATCH] riscv: plic: Honour source priorities
,
Jessica Clarke
,
17:34
[PATCH] riscv: plic: Add a couple of mising sifive_plic_update calls
,
Jessica Clarke
,
17:34
Re: [PATCH] riscv: plic: Add a couple of mising sifive_plic_update calls
,
no-reply
,
17:32
Re: [PATCH v2] riscv: plic: Honour source priorities
,
no-reply
,
16:44
Re: [PATCH] riscv: plic: Honour source priorities
,
no-reply
,
16:00
Re: [PATCH 0/3] Add OpenSBI dynamic firmware support
,
Atish Patra
,
14:19
Re: [PATCH 0/3] Add OpenSBI dynamic firmware support
,
Bin Meng
,
04:56
Re: [PATCH 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Bin Meng
,
04:25
Re: [PATCH 1/3] riscv: Unify Qemu's reset vector code path
,
Bin Meng
,
04:02
Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Bin Meng
,
01:08
June 17, 2020
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
23:48
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
23:32
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
23:22
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Alistair Francis
,
21:45
Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Bin Meng
,
20:41
[PATCH v10 66/73] riscv: convert to cpu_has_work_with_iothread_lock
,
Robert Foley
,
17:05
[PATCH v10 24/73] riscv: convert to cpu_halted
,
Robert Foley
,
17:04
Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Alistair Francis
,
12:40
Re: [PATCH v3 04/11] accel/tcg: Add stub for probe_access()
,
Stefan Hajnoczi
,
09:51
June 16, 2020
Re: [PATCH 0/3] Add OpenSBI dynamic firmware support
,
no-reply
,
18:40
Re: [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support
,
Alistair Francis
,
16:32
Re: [PATCH v6 0/5] RISC-V multi-socket support
,
Alistair Francis
,
16:32
[PATCH 3/3] riscv: Add opensbi firmware dynamic support
,
Atish Patra
,
15:27
[PATCH 2/3] RISC-V: Copy the fdt in dram instead of ROM
,
Atish Patra
,
15:27
[PATCH 1/3] riscv: Unify Qemu's reset vector code path
,
Atish Patra
,
15:27
[PATCH 0/3] Add OpenSBI dynamic firmware support
,
Atish Patra
,
15:27
Re: [PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Alistair Francis
,
14:11
Re: [PATCH v6 4/5] hw/riscv: spike: Allow creating multiple NUMA sockets
,
Alistair Francis
,
13:59
Re: [PATCH v6 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Alistair Francis
,
13:49
Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Alistair Francis
,
13:18
Re: [PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine
,
Alistair Francis
,
13:17
June 15, 2020
[PATCH v6 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
23:23
[PATCH v6 4/5] hw/riscv: spike: Allow creating multiple NUMA sockets
,
Anup Patel
,
23:23
[PATCH v6 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Anup Patel
,
23:23
[PATCH v6 2/5] hw/riscv: Allow creating multiple instances of PLIC
,
Anup Patel
,
23:23
[PATCH v6 1/5] hw/riscv: Allow creating multiple instances of CLINT
,
Anup Patel
,
23:23
[PATCH v6 0/5] RISC-V multi-socket support
,
Anup Patel
,
23:23
[PATCH v2 5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device
,
Bin Meng
,
20:51
[PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state
,
Bin Meng
,
20:51
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries
,
Bin Meng
,
20:51
[PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support
,
Bin Meng
,
20:51
[PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Bin Meng
,
20:50
[PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine
,
Bin Meng
,
20:50
[PULL 21/84] riscv: Fix to put "riscv.hart_array" devices on sysbus
,
Markus Armbruster
,
16:40
[PULL 22/84] riscv: Fix type of SiFive[EU]SocState, member parent_obj
,
Markus Armbruster
,
16:40
Re: [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support
,
Alistair Francis
,
15:40
Re: [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device
,
Alistair Francis
,
15:30
Re: [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries
,
Alistair Francis
,
15:14
Re: [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state
,
Alistair Francis
,
15:13
Re: [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Alistair Francis
,
15:11
Re: [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
,
Alistair Francis
,
12:50
Re: [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
,
Alistair Francis
,
12:48
Re: [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality
,
Alistair Francis
,
12:45
Re: [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
,
Alistair Francis
,
12:37
Re: [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller
,
Alistair Francis
,
12:36
Re: [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property
,
Alistair Francis
,
12:25
Re: [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes
,
Alistair Francis
,
12:22
Re: [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP
,
Alistair Francis
,
12:17
Re: [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
,
Alistair Francis
,
12:16
Re: [PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
,
Alistair Francis
,
12:16
Re: [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
,
Alistair Francis
,
12:15
June 13, 2020
Re: [PATCH v5 4/5] hw/riscv: spike: Allow creating multiple NUMA sockets
,
Atish Patra
,
01:34
Re: [PATCH v5 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Atish Patra
,
01:22
Re: [PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Atish Patra
,
01:18
June 12, 2020
Re: [PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Atish Patra
,
21:13
Re: [PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Alistair Francis
,
21:02
June 11, 2020
Re: [PATCH v2 1/4] riscv: Generalize CPU init routine for the base CPU
,
Alistair Francis
,
12:08
RE: [PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Anup Patel
,
09:11
RE: [PATCH v5 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
09:01
June 10, 2020
Re: [PATCH v9 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
21:12
[PATCH v2 4/4] riscv: Keep the CPU init routine names consistent
,
Bin Meng
,
21:09
[PATCH v2 3/4] riscv: Generalize CPU init routine for the imacu CPU
,
Bin Meng
,
21:09
[PATCH v2 2/4] riscv: Generalize CPU init routine for the gcsu CPU
,
Bin Meng
,
21:09
[PATCH v2 1/4] riscv: Generalize CPU init routine for the base CPU
,
Bin Meng
,
21:09
Re: [PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Alistair Francis
,
19:38
Re: [PATCH v5 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Alistair Francis
,
19:34
Re: [PATCH 4/4] riscv: Keep the CPU init routine names consistent
,
Alistair Francis
,
19:06
Re: [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU
,
Alistair Francis
,
19:05
Re: [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU
,
Alistair Francis
,
19:01
Re: [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU
,
Alistair Francis
,
19:00
Re: [PATCH v1 2/2] sifive_e: Support the revB machine
,
Alistair Francis
,
18:23
[PATCH v6 6/6] target/riscv: Use a smaller guess size for no-MMU PMP
,
Alistair Francis
,
18:21
[PATCH v6 5/6] riscv/opentitan: Connect the UART device
,
Alistair Francis
,
18:21
[PATCH v6 4/6] riscv/opentitan: Connect the PLIC device
,
Alistair Francis
,
18:21
[PATCH v6 3/6] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Alistair Francis
,
18:21
[PATCH v6 2/6] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
18:21
[PATCH v6 1/6] riscv/opentitan: Fix the ROM size
,
Alistair Francis
,
18:21
[PATCH v6 0/6] RISC-V Add the OpenTitan Machine
,
Alistair Francis
,
18:21
Re: [PATCH v9 39/61] target/riscv: vector floating-point compare instructions
,
Richard Henderson
,
13:34
Re: [PATCH v9 00/61] target/riscv: support vector extension v0.7.1
,
no-reply
,
11:37
[PATCH v9 61/61] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
09:40
[PATCH v9 60/61] target/riscv: vector compress instruction
,
LIU Zhiwei
,
09:38
[PATCH v9 59/61] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
09:36
[PATCH v9 58/61] target/riscv: vector slide instructions
,
LIU Zhiwei
,
09:34
[PATCH v9 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
09:32
[PATCH v9 56/61] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
09:30
[PATCH v9 55/61] target/riscv: integer extract instruction
,
LIU Zhiwei
,
09:28
[PATCH v9 54/61] target/riscv: vector element index instruction
,
LIU Zhiwei
,
09:26
[PATCH v9 53/61] target/riscv: vector iota instruction
,
LIU Zhiwei
,
09:24
[PATCH v9 52/61] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
09:22
[PATCH v9 51/61] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
09:20
[PATCH v9 50/61] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
09:18
[PATCH v9 49/61] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
09:16
[PATCH v9 48/61] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
09:14
[PATCH v9 47/61] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
09:12
[PATCH v9 46/61] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
09:10
[PATCH v9 45/61] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
09:08
[PATCH v9 44/61] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
09:06
[PATCH v9 43/61] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
09:04
[PATCH v9 42/61] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
09:02
[PATCH v9 41/61] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
09:00
[PATCH v9 40/61] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
08:58
[PATCH v9 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
08:56
[PATCH v9 38/61] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
08:54
[PATCH v9 37/61] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
08:52
[PATCH v9 36/61] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
08:50
[PATCH v9 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
08:48
[PATCH v9 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
08:46
[PATCH v9 33/61] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
08:44
[PATCH v9 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
08:42
[PATCH v9 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
08:40
[PATCH v9 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
08:38
[PATCH v9 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
08:36
[PATCH v9 28/61] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
08:34
[PATCH v9 27/61] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
08:32
[PATCH v9 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
08:30
[PATCH v9 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
08:28
[PATCH v9 24/61] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
08:26
[PATCH v9 23/61] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
08:24
[PATCH v9 22/61] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
08:22
[PATCH v9 21/61] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
08:20
[PATCH v9 20/61] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
08:18
[PATCH v9 19/61] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
08:16
[PATCH v9 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
08:14
[PATCH v9 17/61] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
08:12
[PATCH v9 16/61] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
08:10
[PATCH v9 15/61] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
08:08
[PATCH v9 14/61] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
08:06
[PATCH v9 13/61] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
08:04
[PATCH v9 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
08:02
[PATCH v9 11/61] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
08:00
[PATCH v9 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
07:58
[PATCH v9 09/61] target/riscv: add vector amo operations
,
LIU Zhiwei
,
07:56
[PATCH v9 08/61] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
07:54
[PATCH v9 07/61] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
07:52
[PATCH v9 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
07:50
[PATCH v9 05/61] target/riscv: add an internals.h header
,
LIU Zhiwei
,
07:48
[PATCH v9 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
07:46
[PATCH v9 03/61] target/riscv: support vector extension csr
,
LIU Zhiwei
,
07:44
[PATCH v9 02/61] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
07:42
[PATCH v9 01/61] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
07:40
[PATCH v9 00/61] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
07:38
June 09, 2020
Re: [PATCH v2] riscv: Add helper to make NaN-boxing for FP register
,
Alistair Francis
,
19:25
Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
,
Alistair Francis
,
19:18
Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
,
Philippe Mathieu-Daudé
,
10:21
Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
,
Damien Hedde
,
09:48
[PATCH v3 19/24] riscv: Fix to put "riscv.hart_array" devices on sysbus
,
Markus Armbruster
,
08:24
[PATCH v3 20/24] riscv: Fix type of SiFive[EU]SocState, member parent_obj
,
Markus Armbruster
,
08:24
Re: [RFC PATCH 00/35] hw/qdev: Warn when using pre-qdev/QOM devices
,
Paolo Bonzini
,
07:14
Re: [RFC PATCH 26/35] hw/openrisc/cputimer: Emit warning when old code is used
,
Paolo Bonzini
,
07:14
Re: [RFC PATCH 27/35] hw/ppc/ppc: Emit warning when old code is used
,
Paolo Bonzini
,
07:13
Re: [RFC PATCH 29/35] hw/ppc/ppc_booke: Emit warning when old code is used
,
Paolo Bonzini
,
07:12
Re: [RFC PATCH 30/35] hw/ppc/virtex_ml507: Emit warning when old code is used
,
Paolo Bonzini
,
07:12
Re: [RFC PATCH 21/35] hw/lm32/lm32_hwsetup: Emit warning when old code is used
,
Paolo Bonzini
,
07:11
Re: [RFC PATCH 20/35] hw/intc/i8259: Emit warning when old code is used
,
Paolo Bonzini
,
07:10
Re: [RFC PATCH 06/35] hw/timer/arm_timer: Emit warning when old code is used
,
Paolo Bonzini
,
07:10
Re: [RFC PATCH 14/35] hw/i386/pc: Emit warning when old code is used
,
Paolo Bonzini
,
07:08
Re: [RFC PATCH 17/35] hw/input/pckbd: Emit warning when old code is used
,
Paolo Bonzini
,
07:07
Re: [RFC PATCH 18/35] hw/input/ps2: Emit warning when old code is used
,
Paolo Bonzini
,
07:07
Re: [RFC PATCH 23/35] hw/misc/applesmc: Emit warning when old code is used
,
Paolo Bonzini
,
07:05
Re: [RFC PATCH 32/35] hw/riscv: Emit warning when old code is used
,
Paolo Bonzini
,
07:04
Re: [RFC PATCH 33/35] hw/timer/slavio_timer: Emit warning when old code is used
,
Paolo Bonzini
,
07:03
Re: [PATCH v2] riscv: Add helper to make NaN-boxing for FP register
,
Chih-Min Chao
,
06:07
June 08, 2020
Re: [RFC PATCH 22/35] hw/m68k/mcf520x: Emit warning when old code is used
,
Thomas Huth
,
16:53
Re: [RFC PATCH 15/35] hw/i386/xen/xen-hvm: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
13:37
RE: [RFC PATCH 15/35] hw/i386/xen/xen-hvm: Emit warning when old code is used
,
Paul Durrant
,
13:00
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
Richard Henderson
,
12:28
Re: [RFC PATCH 00/35] hw/qdev: Warn when using pre-qdev/QOM devices
,
Philippe Mathieu-Daudé
,
12:17
Re: [RFC PATCH 00/35] hw/qdev: Warn when using pre-qdev/QOM devices
,
Peter Maydell
,
12:14
[RFC PATCH 35/35] hw/xtensa/xtfpga: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:04
[RFC PATCH 34/35] hw/usb/hcd-musb: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:04
[RFC PATCH 23/35] hw/misc/applesmc: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:04
[RFC PATCH 33/35] hw/timer/slavio_timer: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:04
[RFC PATCH 32/35] hw/riscv: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:04
[RFC PATCH 31/35] hw/sh4: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 30/35] hw/ppc/virtex_ml507: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 26/35] hw/openrisc/cputimer: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 29/35] hw/ppc/ppc_booke: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 28/35] hw/ppc/ppc4xx: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 24/35] hw/misc/cbus: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 27/35] hw/ppc/ppc: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 25/35] hw/nvram/eeprom93xx: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 22/35] hw/m68k/mcf520x: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 21/35] hw/lm32/lm32_hwsetup: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:03
[RFC PATCH 20/35] hw/intc/i8259: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 19/35] hw/input/tsc2005: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 18/35] hw/input/ps2: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 17/35] hw/input/pckbd: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 16/35] hw/input/lasips2: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 14/35] hw/i386/pc: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 13/35] hw/dma/soc_dma: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 15/35] hw/i386/xen/xen-hvm: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 05/35] hw/arm/nseries: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 12/35] hw/dma/etraxfs_dma: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:02
[RFC PATCH 11/35] hw/display/vga-isa-mm: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 10/35] hw/display/tc6393xb: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 09/35] hw/display/ramfb: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 08/35] hw/display/blizzard: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 07/35] hw/char/parallel: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 03/35] hw/arm/omap: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 06/35] hw/timer/arm_timer: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 04/35] hw/arm/pxa2xx: Emit warning when old code is used
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 00/35] hw/qdev: Warn when using pre-qdev/QOM devices
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 01/35] qom/object: Update documentation
,
Philippe Mathieu-Daudé
,
12:01
[RFC PATCH 02/35] hw/core/qdev: Add qdev_warn_deprecated_function_used() helper
,
Philippe Mathieu-Daudé
,
12:01
[PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device
,
Bin Meng
,
10:18
[PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries
,
Bin Meng
,
10:18
[PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
,
Bin Meng
,
10:18
[PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
,
Bin Meng
,
10:18
[PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state
,
Bin Meng
,
10:18
[PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
,
Bin Meng
,
10:18
[PATCH 09/15] hw/riscv: sifive_u: Add reset functionality
,
Bin Meng
,
10:18
[PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller
,
Bin Meng
,
10:18
[PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property
,
Bin Meng
,
10:18
[PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes
,
Bin Meng
,
10:18
[PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
,
Bin Meng
,
10:18
[PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
,
Bin Meng
,
10:18
[PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP
,
Bin Meng
,
10:18
[PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
,
Bin Meng
,
10:18
[PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
,
Bin Meng
,
10:18
[PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support
,
Bin Meng
,
10:18
June 07, 2020
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
LIU Zhiwei
,
22:39
June 05, 2020
Re: [PATCH v2 04/17] target/riscv: Implement checks for hfence
,
Richard Henderson
,
13:54
Re: [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode
,
Richard Henderson
,
13:52
Re: [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs
,
Richard Henderson
,
13:50
Re: [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs
,
Richard Henderson
,
13:50
[PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU
,
Bin Meng
,
03:40
[PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU
,
Bin Meng
,
03:40
[PATCH 4/4] riscv: Keep the CPU init routine names consistent
,
Bin Meng
,
03:40
[PATCH 1/4] riscv: Generalize CPU init routine for the base CPU
,
Bin Meng
,
03:40
June 04, 2020
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
Richard Henderson
,
23:30
Re: [PATCH v8 40/62] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
22:56
Re: [PATCH v8 58/62] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
22:53
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
LIU Zhiwei
,
22:51
[PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault
,
Alistair Francis
,
21:30
[PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses
,
Alistair Francis
,
21:30
[PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs
,
Alistair Francis
,
21:30
[PATCH v2 14/17] target/riscv: Only support little endian guests
,
Alistair Francis
,
21:30
[PATCH v2 10/17] target/riscv: Fix the interrupt cause code
,
Alistair Francis
,
21:30
[PATCH v2 13/17] target/riscv: Only support a single VSXL length
,
Alistair Francis
,
21:30
[PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA
,
Alistair Francis
,
21:30
[PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst
,
Alistair Francis
,
21:30
[PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions
,
Alistair Francis
,
21:30
[PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
,
Alistair Francis
,
21:30
[PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension
,
Alistair Francis
,
21:30
[PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry
,
Alistair Francis
,
21:30
[PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status
,
Alistair Francis
,
21:29
[PATCH v2 04/17] target/riscv: Implement checks for hfence
,
Alistair Francis
,
21:29
[PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode
,
Alistair Francis
,
21:29
[PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs
,
Alistair Francis
,
21:29
[PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs
,
Alistair Francis
,
21:29
[PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1
,
Alistair Francis
,
21:29
Re: [PATCH v8 58/62] target/riscv: floating-point scalar move instructions
,
Richard Henderson
,
17:32
Re: [PATCH v8 56/62] target/riscv: integer extract instruction
,
Richard Henderson
,
17:05
Re: [PATCH v8 42/62] target/riscv: vector floating-point merge instructions
,
Richard Henderson
,
16:57
Re: [PATCH v8 40/62] target/riscv: vector floating-point compare instructions
,
Richard Henderson
,
16:51
Re: [PATCH v8 26/62] target/riscv: vector single-width fractional multiply with rounding and saturation
,
Richard Henderson
,
16:26
Re: [PATCH v8 25/62] target/riscv: vector single-width averaging add and subtract
,
Richard Henderson
,
16:22
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
Richard Henderson
,
16:15
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
LIU Zhiwei
,
04:33
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
01:55
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
LIU Zhiwei
,
01:40
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
00:45
June 03, 2020
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
LIU Zhiwei
,
21:59
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
12:05
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
LIU Zhiwei
,
06:33
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
LIU Zhiwei
,
01:46
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
Richard Henderson
,
00:28
June 02, 2020
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
14:03
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
13:56
Re: [PATCH v4 00/13] user-mode: Prune build dependencies (part 1)
,
Laurent Vivier
,
11:55
Re: [PATCH v4 00/13] user-mode: Prune build dependencies (part 1)
,
Philippe Mathieu-Daudé
,
10:47
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
LIU Zhiwei
,
08:28
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
LIU Zhiwei
,
07:22
June 01, 2020
Re: [PATCH v4 13/13] stubs: Restrict ui/win32-kbd-hook to system-mode
,
Richard Henderson
,
19:01
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
17:32
Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
,
Alistair Francis
,
17:31
Re: [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init
,
Bin Meng
,
01:26
Re: [PATCH v5 03/11] target/riscv: Disable the MMU correctly
,
Bin Meng
,
01:24
Re: [PATCH v4 4/4] docs: deprecated: Update the -bios documentation
,
Bin Meng
,
00:55
Re: [PATCH v4 3/4] target/riscv: Drop support for ISA spec version 1.09.1
,
Bin Meng
,
00:55
Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
,
Bin Meng
,
00:51
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