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qemu-riscv (date)
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Last Modified: Fri Apr 30 2021 03:13:34 -0400
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April 30, 2021
[PATCH v2 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot
,
Bin Meng
,
03:13
[PATCH v2 7/8] hw/riscv: Use macros for BIOS image names
,
Bin Meng
,
03:13
[PATCH v2 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage
,
Bin Meng
,
03:13
[PATCH v2 5/8] docs/system/riscv: Correct the indentation level of supported devices
,
Bin Meng
,
03:13
[PATCH v2 4/8] hw/riscv: Support the official PLIC DT bindings
,
Bin Meng
,
03:13
[PATCH v2 3/8] hw/riscv: Support the official CLINT DT bindings
,
Bin Meng
,
03:13
[PATCH v2 2/8] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
,
Bin Meng
,
03:13
[PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
,
Bin Meng
,
03:13
[PATCH] docs/system: riscv: Include shakti_c machine documentation
,
Bin Meng
,
03:05
Re: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
,
Anup Patel
,
00:54
April 28, 2021
Re: [PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
,
Eduardo Habkost
,
14:50
Re: [PATCH 7/7] hw/nvram: Do not build FW_CFG if not required
,
Philippe Mathieu-Daudé
,
13:29
Re: [PATCH 6/7] hw/{arm,hppa,riscv}: Add fw_cfg arch-specific stub
,
Philippe Mathieu-Daudé
,
13:23
Re: [PATCH 6/7] hw/{arm,hppa,riscv}: Add fw_cfg arch-specific stub
,
Laszlo Ersek
,
12:44
Re: [PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
,
Laszlo Ersek
,
12:33
Re: [PATCH 4/7] hw/acpi/vmgenid: Make ACPI_VMGENID depends on FW_CFG Kconfig
,
Laszlo Ersek
,
12:25
Re: [PATCH 1/7] stubs: Restrict fw_cfg stubs to sysemu
,
Laszlo Ersek
,
12:23
[PATCH] target/riscv: Dump CSR mscratch/sscratch/satp
,
Changbin Du
,
08:57
[PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
00:19
[PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
00:19
[PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alexey Baturo
,
00:19
[PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
00:19
[PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
00:18
[PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
,
Alexey Baturo
,
00:18
[PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
00:18
[PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
00:07
April 27, 2021
[PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
23:56
Re: [PATCH v8 0/6] RISC-V Pointer Masking implementation
,
no-reply
,
18:19
[PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
,
Alexey Baturo
,
18:06
[PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
,
Alexey Baturo
,
18:06
[PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
,
Alexey Baturo
,
18:06
[PATCH v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alexey Baturo
,
18:06
[PATCH v8 0/6] RISC-V Pointer Masking implementation
,
Alexey Baturo
,
18:06
[PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
,
Alexey Baturo
,
18:06
[PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
,
Alexey Baturo
,
18:06
Re: [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros
,
Frank Chang
,
03:14
Re: [PATCH v2] target/riscv: fix wfi exception behavior
,
Alistair Francis
,
02:09
Re: [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions
,
Alistair Francis
,
02:07
Re: [PATCH v5 06/17] target/riscv: rvb: min/max instructions
,
Alistair Francis
,
02:06
Re: [PATCH v5 05/17] target/riscv: rvb: pack two words into one register
,
Alistair Francis
,
02:06
Re: [PATCH v5 04/17] target/riscv: rvb: logic-with-negate
,
Alistair Francis
,
02:05
Re: [PATCH v5 03/17] target/riscv: rvb: count bits set
,
Alistair Francis
,
02:03
Re: [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros
,
Alistair Francis
,
02:02
April 26, 2021
Re: [PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
,
David Gibson
,
21:57
Re: [PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
,
David Gibson
,
21:57
Re: [PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
,
BALATON Zoltan
,
18:04
[PATCH 7/7] hw/nvram: Do not build FW_CFG if not required
,
Philippe Mathieu-Daudé
,
15:36
[PATCH 6/7] hw/{arm,hppa,riscv}: Add fw_cfg arch-specific stub
,
Philippe Mathieu-Daudé
,
15:36
[PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
,
Philippe Mathieu-Daudé
,
15:35
[PATCH 4/7] hw/acpi/vmgenid: Make ACPI_VMGENID depends on FW_CFG Kconfig
,
Philippe Mathieu-Daudé
,
15:35
[PATCH 3/7] hw/nvram: Declare FW_CFG_DMA Kconfig symbol in hw/nvram/
,
Philippe Mathieu-Daudé
,
15:35
[PATCH 2/7] hw/nvram: Rename FW_CFG_MIPS as generic FW_CFG Kconfig symbol
,
Philippe Mathieu-Daudé
,
15:35
[PATCH 1/7] stubs: Restrict fw_cfg stubs to sysemu
,
Philippe Mathieu-Daudé
,
15:35
[PATCH 0/7] hw/nvram/fw_cfg: Do not build device if not needed (Spring cleanup)
,
Philippe Mathieu-Daudé
,
15:35
Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
,
Philippe Mathieu-Daudé
,
12:51
Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
,
Dr. David Alan Gilbert
,
12:15
Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
,
Alistair Francis
,
01:34
April 25, 2021
Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
,
Richard Henderson
,
19:53
Re: [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
,
Alistair Francis
,
18:59
Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
,
Alistair Francis
,
18:58
Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
,
Alistair Francis
,
18:58
April 24, 2021
Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
,
Richard Henderson
,
13:14
Re: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
,
Richard Henderson
,
13:08
April 23, 2021
[PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
,
Alistair Francis
,
23:34
[PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions
,
Alistair Francis
,
23:34
[PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
,
Alistair Francis
,
23:34
[PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro
,
Alistair Francis
,
23:34
[PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro
,
Alistair Francis
,
23:34
[PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro
,
Alistair Francis
,
23:33
[PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Alistair Francis
,
23:33
[PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro
,
Alistair Francis
,
23:33
[PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro
,
Alistair Francis
,
23:31
[PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro
,
Alistair Francis
,
23:29
[PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
,
Alistair Francis
,
23:28
April 22, 2021
Re: [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
,
Richard Henderson
,
21:25
Re: [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
,
Richard Henderson
,
21:16
Re: [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
,
Richard Henderson
,
21:12
Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
,
Richard Henderson
,
21:08
[PATCH v6 18/18] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 17/18] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 16/18] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 15/18] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 14/18] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 13/18] cpu: Move CPUClass::write_elf* to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 12/18] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 11/18] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 09/18] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
15:40
[PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 05/18] cpu: Directly use get_memory_mapping() fallback handlers in place
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 04/18] cpu: Directly use get_paging_enabled() fallback handlers in place
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 03/18] cpu: Directly use cpu_write_elf*() fallback handlers in place
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 02/18] cpu: Introduce cpu_virtio_is_big_endian()
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 01/18] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
,
Philippe Mathieu-Daudé
,
15:39
[PATCH v6 00/18] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
15:39
Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Philippe Mathieu-Daudé
,
12:05
Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Peter Maydell
,
11:54
Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Philippe Mathieu-Daudé
,
11:42
Re: [PATCH v5 07/15] cpu: Move CPUClass::vmsd to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
07:05
Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Philippe Mathieu-Daudé
,
07:01
[PATCH v5 15/15] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v5 14/15] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v5 13/15] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v5 12/15] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v5 11/15] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v5 10/15] cpu: Move CPUClass::write_elf* to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v5 09/15] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v5 08/15] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 07/15] cpu: Move CPUClass::vmsd to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 06/15] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 05/15] cpu: Directly use get_memory_mapping() fallback handlers in place
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 04/15] cpu: Directly use get_paging_enabled() fallback handlers in place
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 03/15] cpu: Directly use cpu_write_elf*() fallback handlers in place
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 02/15] cpu: Introduce cpu_virtio_is_big_endian()
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 01/15] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
,
Philippe Mathieu-Daudé
,
06:47
[PATCH v5 00/15] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
06:47
Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Peter Maydell
,
06:29
Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Philippe Mathieu-Daudé
,
05:55
April 21, 2021
Re: [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
,
Alistair Francis
,
22:02
Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
Alistair Francis
,
21:42
Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
Richard Henderson
,
21:06
Re: [PATCH] target/riscv: fix a typo with interrupt names
,
Alistair Francis
,
20:24
Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification
,
Alistair Francis
,
20:22
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Alistair Francis
,
20:17
Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
Alistair Francis
,
20:05
Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Eduardo Habkost
,
18:03
[RFC] target/riscv: generated RISCV isa string and subset naming convention
,
Emmanuel Blot
,
10:18
[PATCH] target/riscv: fix a typo with interrupt names
,
Emmanuel Blot
,
09:33
[PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option
,
frank . chang
,
00:15
[PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line
,
frank . chang
,
00:15
[PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend
,
frank . chang
,
00:15
[PATCH v5 14/17] target/riscv: rvb: address calculation
,
frank . chang
,
00:14
[PATCH v5 13/17] target/riscv: rvb: generalized or-combine
,
frank . chang
,
00:14
[PATCH v5 12/17] target/riscv: rvb: generalized reverse
,
frank . chang
,
00:14
[PATCH v5 11/17] target/riscv: rvb: rotate (left/right)
,
frank . chang
,
00:14
[PATCH v5 10/17] target/riscv: rvb: shift ones
,
frank . chang
,
00:14
[PATCH v5 09/17] target/riscv: rvb: single-bit instructions
,
frank . chang
,
00:14
[PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
,
frank . chang
,
00:14
[PATCH v5 07/17] target/riscv: rvb: sign-extend instructions
,
frank . chang
,
00:14
[PATCH v5 06/17] target/riscv: rvb: min/max instructions
,
frank . chang
,
00:14
[PATCH v5 05/17] target/riscv: rvb: pack two words into one register
,
frank . chang
,
00:14
[PATCH v5 04/17] target/riscv: rvb: logic-with-negate
,
frank . chang
,
00:14
[PATCH v5 03/17] target/riscv: rvb: count bits set
,
frank . chang
,
00:14
[PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros
,
frank . chang
,
00:14
[PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension
,
frank . chang
,
00:14
[PATCH v5 00/17] support subsets of bitmanip extension
,
frank . chang
,
00:14
April 20, 2021
[PATCH v2] target/riscv: fix wfi exception behavior
,
Jose Martins
,
17:37
Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
Richard Henderson
,
10:17
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Peter Maydell
,
08:40
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Philippe Mathieu-Daudé
,
08:31
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Arnd Bergmann
,
08:27
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Philippe Mathieu-Daudé
,
07:52
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Michael S. Tsirkin
,
06:24
Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification
,
LIU Zhiwei
,
03:20
Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification
,
Alistair Francis
,
02:27
April 19, 2021
Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification
,
LIU Zhiwei
,
21:45
[PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
frank . chang
,
21:31
Re: [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
Frank Chang
,
21:18
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
20:57
Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
LIU Zhiwei
,
20:49
Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification
,
Alistair Francis
,
19:31
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Alistair Francis
,
19:26
Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
Alistair Francis
,
19:24
Re: [PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1
,
Alistair Francis
,
19:14
Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
,
Alistair Francis
,
17:37
Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
,
Alexander Wagner
,
17:26
Re: [PATCH] target/riscv: fix vrgather macro index variable type bug
,
Richard Henderson
,
11:30
Re: [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
Richard Henderson
,
11:28
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Peter Maydell
,
09:43
Re: [PATCH] target/riscv: fix vssub.vv saturation bug
,
Alistair Francis
,
04:50
Re: [PATCH v4 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Bin Meng
,
03:06
Re: [PATCH] target/riscv: fix vssub.vv saturation bug
,
Frank Chang
,
02:31
Re: [PATCH] target/riscv: fix vssub.vv saturation bug
,
Alistair Francis
,
02:26
[PATCH v4 8/8] target/riscv: Add ePMP support for the Ibex CPU
,
Alistair Francis
,
02:19
[PATCH v4 7/8] target/riscv/pmp: Remove outdated comment
,
Alistair Francis
,
02:18
[PATCH v4 6/8] target/riscv: Add a config option for ePMP
,
Alistair Francis
,
02:17
[PATCH v4 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Alistair Francis
,
02:17
[PATCH v4 4/8] target/riscv: Add ePMP CSR access functions
,
Alistair Francis
,
02:17
[PATCH v4 3/8] target/riscv: Add the ePMP feature
,
Alistair Francis
,
02:17
[PATCH v4 2/8] target/riscv: Define ePMP mseccfg
,
Alistair Francis
,
02:16
[PATCH v4 1/8] target/riscv: Fix the PMP is locked check when using TOR
,
Alistair Francis
,
02:16
[PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1
,
Alistair Francis
,
02:16
[PATCH] target/riscv: fix vrgather macro index variable type bug
,
frank . chang
,
02:03
[PATCH] target/riscv: fix vssub.vv saturation bug
,
frank . chang
,
02:02
[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
,
frank . chang
,
01:56
April 16, 2021
Re: [PATCH] target/riscv: fix wfi exception behavior
,
Jose Martins
,
07:34
Re: [PATCH] target/riscv: fix wfi exception behavior
,
Alistair Francis
,
00:55
April 15, 2021
Re: [PATCH] docs: Add documentation for shakti_c machine
,
Alistair Francis
,
18:34
Re:
,
Alistair Francis
,
18:28
Re:
,
Palmer Dabbelt
,
12:07
[no subject]
,
Emmanuel Blot
,
09:42
Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2
,
LIU Zhiwei
,
01:51
Re: [PATCH] docs: Add documentation for shakti_c machine
,
Alistair Francis
,
00:48
Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2
,
Alistair Francis
,
00:46
Re: [PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Alistair Francis
,
00:17
April 14, 2021
Re: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
,
Alistair Francis
,
18:50
Re: [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM
,
Alistair Francis
,
18:49
Re: [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers
,
Alistair Francis
,
18:46
Re: [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers
,
Alistair Francis
,
18:40
Re: [PATCH RFC v5 09/12] target/riscv: Add host cpu type
,
Alistair Francis
,
18:34
Re: [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Alistair Francis
,
18:32
Re: [PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro
,
Bin Meng
,
04:00
Re: [PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro
,
Bin Meng
,
04:00
Re: [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro
,
Bin Meng
,
04:00
Re: [PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro
,
Bin Meng
,
04:00
Re: [PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro
,
Bin Meng
,
04:00
Re: [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro
,
Bin Meng
,
03:59
Re: [PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Bin Meng
,
03:35
April 13, 2021
Re: [PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions
,
Richard Henderson
,
23:58
Re: [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
,
Richard Henderson
,
23:43
Re: [PATCH] target/riscv: fix exception index on instruction access fault
,
Palmer Dabbelt
,
23:42
Re: [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro
,
Richard Henderson
,
23:14
Re: [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Richard Henderson
,
23:13
[PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions
,
Alistair Francis
,
19:38
[PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Alistair Francis
,
19:38
[PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro
,
Alistair Francis
,
19:35
[PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
,
Alistair Francis
,
19:35
[PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro
,
Alistair Francis
,
19:34
[PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro
,
Alistair Francis
,
19:34
[PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro
,
Alistair Francis
,
19:34
[PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro
,
Alistair Francis
,
19:33
[PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro
,
Alistair Francis
,
19:33
[PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on
,
Alistair Francis
,
19:33
[PATCH] target/riscv: fix exception index on instruction access fault
,
Emmanuel Blot
,
12:30
Fix exception index on instruction access fault
,
Emmanuel Blot
,
12:24
April 12, 2021
Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2
,
LIU Zhiwei
,
23:28
[PATCH v3 8/8] target/riscv: Add ePMP support for the Ibex CPU
,
Alistair Francis
,
22:47
[PATCH v3 7/8] target/riscv/pmp: Remove outdated comment
,
Alistair Francis
,
22:43
[PATCH v3 6/8] target/riscv: Add a config option for ePMP
,
Alistair Francis
,
22:43
[PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Alistair Francis
,
22:42
[PATCH v3 3/8] target/riscv: Add the ePMP feature
,
Alistair Francis
,
22:42
[PATCH v3 4/8] target/riscv: Add ePMP CSR access functions
,
Alistair Francis
,
22:42
[PATCH v3 2/8] target/riscv: Define ePMP mseccfg
,
Alistair Francis
,
22:42
[PATCH v3 1/8] target/riscv: Fix the PMP is locked check when using TOR
,
Alistair Francis
,
22:42
[PATCH v3 0/8] RISC-V: Add support for ePMP v0.9.1
,
Alistair Francis
,
22:42
[PATCH] docs: Add documentation for shakti_c machine
,
Vijai Kumar K
,
13:43
Re: [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro
,
Bin Meng
,
05:11
Re: [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro
,
Bin Meng
,
05:11
Re: [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro
,
Bin Meng
,
05:11
Re: [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro
,
Bin Meng
,
05:11
[PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization
,
Yifei Jiang
,
02:53
[PATCH RFC v5 09/12] target/riscv: Add host cpu type
,
Yifei Jiang
,
02:53
[PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Yifei Jiang
,
02:53
[PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Yifei Jiang
,
02:53
[PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
,
Yifei Jiang
,
02:53
[PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
02:53
[PATCH RFC v5 00/12] Add riscv kvm accel support
,
Yifei Jiang
,
02:53
[PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
02:53
[PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
02:53
[PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
02:53
[PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
02:53
[PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
02:53
[PATCH RFC v5 01/12] linux-header: Update linux/kvm.h
,
Yifei Jiang
,
02:53
April 11, 2021
Re: [PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Alistair Francis
,
19:04
Re: [PATCH v2 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Alistair Francis
,
00:06
April 10, 2021
[PATCH] target/riscv: fix wfi exception behavior
,
Jose Martins
,
15:41
April 09, 2021
medeleg[11] should be hardwired to zero?
,
Evan M
,
16:16
Re: [PATCH v2 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Bin Meng
,
10:33
[PATCH v2 7/8] target/riscv/pmp: Remove outdated comment
,
Alistair Francis
,
08:23
[PATCH v2 8/8] target/riscv: Add ePMP support for the Ibex CPU
,
Alistair Francis
,
08:23
[PATCH v2 6/8] target/riscv: Add a config option for ePMP
,
Alistair Francis
,
08:23
[PATCH v2 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Alistair Francis
,
08:22
[PATCH v2 2/8] target/riscv: Define ePMP mseccfg
,
Alistair Francis
,
08:22
[PATCH v2 4/8] target/riscv: Add ePMP CSR access functions
,
Alistair Francis
,
08:22
[PATCH v2 3/8] target/riscv: Add the ePMP feature
,
Alistair Francis
,
08:22
[PATCH v2 0/8] RISC-V: Add support for ePMP v0.9.1
,
Alistair Francis
,
08:22
[PATCH v2 1/8] target/riscv: Fix the PMP is locked check when using TOR
,
Alistair Francis
,
08:22
[RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
03:49
[RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
,
LIU Zhiwei
,
03:49
[RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
LIU Zhiwei
,
03:49
[RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
,
LIU Zhiwei
,
03:49
[RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
,
LIU Zhiwei
,
03:49
Re: [PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Bin Meng
,
00:25
April 08, 2021
Re: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Richard Henderson
,
14:52
Re: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Alistair Francis
,
11:23
Re: [PATCH v1 4/8] target/riscv: Add ePMP CSR access functions
,
Bin Meng
,
08:57
Re: [PATCH v1 1/8] target/riscv: Fix the PMP is locked check when using TOR
,
Bin Meng
,
05:26
April 07, 2021
Re: [ RFC 3/6] target/riscv: Support mcycle/minstret write operation
,
Alistair Francis
,
13:37
Re: [ RFC 4/6] target/riscv: Add support for hpmcounters/hpmevents
,
Alistair Francis
,
13:36
Re: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Alistair Francis
,
13:13
Re: [PATCH] riscv: don't look at SUM when accessing memory from a debugger context
,
Alistair Francis
,
10:53
Re: [PATCH] riscv: don't look at SUM when accessing memory from a debugger context
,
Alistair Francis
,
10:37
Re: [PATCH v1 8/8] target/riscv: Add ePMP support for the Ibex CPU
,
Bin Meng
,
10:29
Re: [PATCH v1 7/8] target/riscv/pmp: Remove outdated comment
,
Bin Meng
,
10:28
Re: [PATCH v1 6/8] target/riscv: Add a config option for ePMP
,
Bin Meng
,
10:28
Re: [PATCH v1 1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine
,
Alistair Francis
,
10:28
Re: [PATCH v1 1/1] hw/opentitan: Update the interrupt layout
,
Alistair Francis
,
10:27
Re: [PATCH v1 1/1] MAINTAINERS: Update the RISC-V CPU Maintainers
,
Alistair Francis
,
10:26
Re: [PATCH v1 3/8] target/riscv: Add the ePMP feature
,
Bin Meng
,
10:24
Re: [PATCH v1 2/8] target/riscv: Define ePMP mseccfg
,
Bin Meng
,
10:24
Re: [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use
,
Alistair Francis
,
09:58
Re: [PATCH v1 2/2] sifive_u: Connect the SiFive PWM device
,
Bin Meng
,
09:55
Re: [PATCH v1 1/2] sifive_u_pwm: Initial commit
,
Bin Meng
,
09:55
Re: [PATCH v1 1/1] MAINTAINERS: Update the RISC-V CPU Maintainers
,
Philippe Mathieu-Daudé
,
08:15
Re: [PATCH v1 1/1] MAINTAINERS: Update the RISC-V CPU Maintainers
,
Bastian Koppelmann
,
04:15
April 06, 2021
Re: [PATCH v1 1/1] MAINTAINERS: Update the RISC-V CPU Maintainers
,
Bin Meng
,
21:40
[PATCH v1 1/1] MAINTAINERS: Update the RISC-V CPU Maintainers
,
Alistair Francis
,
18:51
Re: [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build
,
Richard Henderson
,
10:57
[PATCH] riscv: don't look at SUM when accessing memory from a debugger context
,
Jade Fink
,
09:10
Re: [PATCH v1 1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine
,
Bin Meng
,
04:42
Re: [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access
,
Bin Meng
,
04:35
Re: [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions
,
Bin Meng
,
04:35
Re: [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations
,
Bin Meng
,
04:35
Re: [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates
,
Bin Meng
,
04:34
Re: [PATCH v1 1/1] hw/opentitan: Update the interrupt layout
,
Bin Meng
,
04:32
April 05, 2021
Re: Handling Timer Interrupts in Supervisor Mode (machine virt)
,
Alek Fröhlich
,
13:02
Handling Timer Interrupts in Supervisor Mode (machine virt)
,
Alek Fröhlich
,
12:14
Re: [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro
,
Richard Henderson
,
11:16
Re: [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro
,
Richard Henderson
,
11:15
Re: [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro
,
Richard Henderson
,
11:15
Re: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Richard Henderson
,
11:10
Re: [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro
,
Richard Henderson
,
10:54
Re: [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro
,
Richard Henderson
,
10:49
Re: [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro
,
Richard Henderson
,
10:48
April 04, 2021
Re: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M
,
Vijai Kumar K
,
07:43
April 02, 2021
Re: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M
,
Alistair Francis
,
16:07
[PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build
,
Alistair Francis
,
16:05
[PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro
,
Alistair Francis
,
16:05
[PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro
,
Alistair Francis
,
16:05
[PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro
,
Alistair Francis
,
16:04
[PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
,
Alistair Francis
,
16:04
[PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro
,
Alistair Francis
,
16:04
[PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro
,
Alistair Francis
,
16:04
[PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro
,
Alistair Francis
,
16:04
[PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on
,
Alistair Francis
,
16:04
Re: [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access
,
Richard Henderson
,
13:19
Re: [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations
,
Richard Henderson
,
13:17
Re: [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions
,
Richard Henderson
,
13:14
Re: [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates
,
Richard Henderson
,
13:14
Re: [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum
,
Richard Henderson
,
13:11
Re: [PATCH v3 3/4] hw/char: Add Shakti UART emulation
,
Alistair Francis
,
12:14
Re: [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform
,
Vijai Kumar K
,
11:41
Re: [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform
,
Alistair Francis
,
09:07
Re: [PATCH v3 1/4] target/riscv: Add Shakti C class CPU
,
Alistair Francis
,
09:06
Re: [PATCH v3 2/4] riscv: Add initial support for Shakti C machine
,
Alistair Francis
,
09:06
[PATCH v1 8/8] target/riscv: Add ePMP support for the Ibex CPU
,
Alistair Francis
,
08:50
[PATCH v1 7/8] target/riscv/pmp: Remove outdated comment
,
Alistair Francis
,
08:50
[PATCH v1 6/8] target/riscv: Add a config option for ePMP
,
Alistair Francis
,
08:50
[PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
,
Alistair Francis
,
08:50
[PATCH v1 4/8] target/riscv: Add ePMP CSR access functions
,
Alistair Francis
,
08:49
[PATCH v1 1/8] target/riscv: Fix the PMP is locked check when using TOR
,
Alistair Francis
,
08:49
[PATCH v1 3/8] target/riscv: Add the ePMP feature
,
Alistair Francis
,
08:49
[PATCH v1 2/8] target/riscv: Define ePMP mseccfg
,
Alistair Francis
,
08:49
[PATCH v1 0/8] RISC-V: Add support for ePMP v0.9.1
,
Alistair Francis
,
08:49
[PATCH v1 2/2] sifive_u: Connect the SiFive PWM device
,
Alistair Francis
,
08:46
[PATCH v1 1/2] sifive_u_pwm: Initial commit
,
Alistair Francis
,
08:46
[PATCH v1 0/2] Add the SiFive PWM device
,
Alistair Francis
,
08:45
[PATCH v1 1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine
,
Alistair Francis
,
08:44
April 01, 2021
[PATCH v3 3/4] hw/char: Add Shakti UART emulation
,
Vijai Kumar K
,
14:15
[PATCH v3 2/4] riscv: Add initial support for Shakti C machine
,
Vijai Kumar K
,
14:15
[PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform
,
Vijai Kumar K
,
14:15
[PATCH v3 0/4] Add support for Shakti SoC from IIT-M
,
Vijai Kumar K
,
14:15
[PATCH v3 1/4] target/riscv: Add Shakti C class CPU
,
Vijai Kumar K
,
14:15
Re: [PATCH v2 2/4] riscv: Add initial support for Shakti C machine
,
Vijai Kumar K
,
13:44
Re: [PATCH v2 2/4] riscv: Add initial support for Shakti C machine
,
Alistair Francis
,
13:23
Re: [PATCH v2 2/4] riscv: Add initial support for Shakti C machine
,
Vijai Kumar K
,
13:18
[PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access
,
Alistair Francis
,
11:20
[PATCH v2 0/5] RISC-V: Convert the CSR access functions to use
,
Alistair Francis
,
11:20
[PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations
,
Alistair Francis
,
11:20
[PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates
,
Alistair Francis
,
11:20
[PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum
,
Alistair Francis
,
11:19
[PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions
,
Alistair Francis
,
11:19
Re: [RFC v2 0/4] target/riscv: add RNMI support
,
Frank Chang
,
05:36
[RFC v2 4/4] target/riscv: add RNMI mnret instruction
,
frank . chang
,
05:27
[RFC v2 3/4] target/riscv: handle RNMI interrupt and exception
,
frank . chang
,
05:27
[RFC v2 2/4] target/riscv: add RNMI CSRs
,
frank . chang
,
05:27
[RFC v2 1/4] target/riscv: add RNMI cpu feature
,
frank . chang
,
05:27
[RFC v2 0/4] target/riscv: add RNMI support
,
frank . chang
,
05:27
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