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qemu-riscv (date)
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Last Modified: Thu Jul 04 2024 00:02:35 -0400
Messages in reverse chronological order
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July 04, 2024
[PATCH 2/2] target/riscv: Add textra matching condition for the triggers
,
Alvin Chang
,
00:02
[PATCH 1/2] target/riscv: Preliminary textra trigger CSR writting support
,
Alvin Chang
,
00:02
[PATCH 0/2] RISC-V: Add preliminary textra trigger CSR functions
,
Alvin Chang
,
00:02
July 03, 2024
[PATCH 5/8] i386/cpu: Support thread and module level cache topology
,
Zhao Liu
,
23:01
[PATCH 8/8] qemu-options: Add the description of smp-cache object
,
Zhao Liu
,
23:01
[PATCH 7/8] i386/pc: Support cache topology in -machine for PC machine
,
Zhao Liu
,
23:01
[PATCH 4/8] hw/core: Check smp cache topology support for machine
,
Zhao Liu
,
23:01
[PATCH 6/8] i386/cpu: Update cache topology with machine's configuration
,
Zhao Liu
,
23:01
[PATCH 3/8] hw/core: Add smp cache topology for machine
,
Zhao Liu
,
23:00
[PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
23:00
[PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic
,
Zhao Liu
,
23:00
[PATCH 0/8] Introduce SMP Cache Topology
,
Zhao Liu
,
23:00
[PATCH] hw/intc: sifive_plic: Fix heap-buffer-overflow in SiFive PLIC read operation
,
Zheyu Ma
,
18:03
Re: [PATCH v4 02/14] hw/riscv: add riscv-iommu-bits.h
,
Daniel Henrique Barboza
,
16:21
Re: [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
Richard Henderson
,
12:49
Re: [PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
Richard Henderson
,
12:48
Re: [PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
11:07
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Sunil V L
,
10:57
[PATCH v3 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
10:55
[PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
10:54
[PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
10:53
[PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
10:53
[PATCH v3 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
10:52
[PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
10:52
[PATCH v3 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
10:51
[PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
10:51
Re: [PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Philippe Mathieu-Daudé
,
09:08
[PATCH v2 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
08:40
[PATCH v2 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
08:39
[PATCH v2 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
08:39
[PATCH v2 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
08:38
[PATCH v2 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
08:38
[PATCH v2 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
08:37
[PATCH v2 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
08:37
[PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
08:36
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Sunil V L
,
06:23
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
LIU Zhiwei
,
04:48
[RFC PATCH v4 2/2] tests/qtest: QTest example for RISC-V CSR register
,
Ivan Klokov
,
04:20
[RFC PATCH v4 1/2] target/riscv: Add RISC-V CSR qtest support
,
Ivan Klokov
,
04:20
[RFC PATCH v4 0/2] Support RISC-V CSR read/write in Qtest environment
,
Ivan Klokov
,
04:20
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Philippe Mathieu-Daudé
,
03:33
July 02, 2024
Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
22:48
Re: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Alistair Francis
,
22:36
Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
Alistair Francis
,
22:33
Re: [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
Alistair Francis
,
22:28
Re: [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
Alistair Francis
,
22:27
Re: [PATCH] disas/riscv: Add decode for Zawrs extension
,
Alistair Francis
,
22:21
Re: [PATCH] disas/riscv: Add decode for Zawrs extension
,
Alistair Francis
,
22:13
Re: [PATCH v3 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
Alistair Francis
,
22:11
Re: [PATCH v7 07/11] target/riscv: Save counter values during countinhibit update
,
Alistair Francis
,
22:04
Re: [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties
,
Alistair Francis
,
22:03
[PATCH v3 05/11] target/riscv: Support Zama16b extension
,
LIU Zhiwei
,
21:56
[PATCH v3 11/11] disas/riscv: Support zabha disassemble
,
LIU Zhiwei
,
21:54
[PATCH v3 10/11] target/riscv: Expose zabha extension as a cpu property
,
LIU Zhiwei
,
21:53
[PATCH v3 09/11] target/riscv: Add amocas.[b|h] for Zabha
,
LIU Zhiwei
,
21:53
[PATCH v3 08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
,
LIU Zhiwei
,
21:52
[PATCH v3 07/11] target/riscv: Add AMO instructions for Zabha
,
LIU Zhiwei
,
21:51
[PATCH v3 06/11] target/riscv: Move gen_amo before implement Zabha
,
LIU Zhiwei
,
21:51
[PATCH v3 04/11] disas/riscv: Support zcmop disassemble
,
LIU Zhiwei
,
21:50
[PATCH v3 03/11] target/riscv: Add zcmop extension
,
LIU Zhiwei
,
21:49
[PATCH v3 02/11] disas/riscv: Support zimop disassemble
,
LIU Zhiwei
,
21:49
[PATCH v3 01/11] target/riscv: Add zimop extension
,
LIU Zhiwei
,
21:48
[PATCH v3 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
LIU Zhiwei
,
21:48
Re: [PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret
,
Alistair Francis
,
21:25
Re: [PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support
,
Alistair Francis
,
21:19
Re: [PATCH v7 04/11] target/riscv: Add cycle & instret privilege mode filtering definitions
,
Alistair Francis
,
21:13
Re: [PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.
,
Alistair Francis
,
21:07
Re: [PATCH v2 10/11] target/riscv: Enable zabha for max cpu
,
Alistair Francis
,
20:29
Re: [PATCH v2 05/11] target/riscv: Support Zama16b extension
,
Alistair Francis
,
20:12
Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
,
Alistair Francis
,
19:59
Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame
,
Alistair Francis
,
19:57
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Alistair Francis
,
19:56
Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
,
Richard Henderson
,
19:08
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Richard Henderson
,
19:04
Re: [PATCH v2 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
Deepak Gupta
,
18:34
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Daniel Henrique Barboza
,
18:17
Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame
,
Daniel Henrique Barboza
,
18:16
Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
,
Daniel Henrique Barboza
,
18:16
Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame
,
Philippe Mathieu-Daudé
,
15:58
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Philippe Mathieu-Daudé
,
15:56
Re: [PATCH 0/3] util: Add cpuinfo support for riscv
,
Richard Henderson
,
12:26
Re: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Philippe Mathieu-Daudé
,
10:19
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Jonathan Cameron
,
10:02
Re: [PATCH v4 06/16] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Sunil V L
,
04:33
Re: [PATCH v4 06/16] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Igor Mammedov
,
04:30
July 01, 2024
Re: [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
21:50
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Michael S. Tsirkin
,
17:04
Re: [PATCH v7 11/11] target/riscv: Do not setup pmu timer if OF is disabled
,
Daniel Henrique Barboza
,
15:39
Re: [PATCH v7 10/11] target/riscv: More accurately model priv mode filtering.
,
Daniel Henrique Barboza
,
15:38
Re: [PATCH v7 09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit
,
Daniel Henrique Barboza
,
15:37
Re: [PATCH v7 07/11] target/riscv: Save counter values during countinhibit update
,
Daniel Henrique Barboza
,
15:34
Re: [PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret
,
Daniel Henrique Barboza
,
15:30
Re: [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties
,
Daniel Henrique Barboza
,
15:10
Re: [PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.
,
Daniel Henrique Barboza
,
14:21
Re: [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
Philippe Mathieu-Daudé
,
11:10
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