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qemu-riscv (date)
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Last Modified: Wed Mar 31 2021 12:08:05 -0400
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March 31, 2021
Re: [PATCH 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
,
Richard Henderson
,
12:08
Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
,
Alistair Francis
,
11:53
Re: [PATCH 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot
,
Alistair Francis
,
11:52
Re: [PATCH 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage
,
Alistair Francis
,
11:48
Re: [PATCH 7/8] hw/riscv: Use macros for BIOS image names
,
Alistair Francis
,
11:47
Re: [PATCH 5/8] docs/system/riscv: Correct the indentation level of supported devices
,
Alistair Francis
,
11:46
Re: [PATCH 4/8] hw/riscv: Support the official PLIC DT bindings
,
Alistair Francis
,
11:45
Re: [PATCH 3/8] hw/riscv: Support the official CLINT DT bindings
,
Alistair Francis
,
11:45
Re: [PATCH 2/8] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
,
Alistair Francis
,
11:44
Re: [PATCH 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
,
Alistair Francis
,
11:43
Re: [PATCH v2 4/4] hw/riscv: Connect Shakti UART to Shakti platform
,
Alistair Francis
,
11:41
Re: [PATCH v2 3/4] hw/char: Add Shakti UART emulation
,
Alistair Francis
,
11:41
Re: [PATCH v2 2/4] riscv: Add initial support for Shakti C machine
,
Alistair Francis
,
11:38
Re: [ RFC 2/6] target/riscv: Implement mcountinhibit CSR
,
Alistair Francis
,
11:31
Re: [PATCH] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
,
Alistair Francis
,
11:28
Re: [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64
,
Alistair Francis
,
11:06
Re: [PATCH] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
,
Alistair Francis
,
11:04
[PATCH v1 1/1] hw/opentitan: Update the interrupt layout
,
Alistair Francis
,
11:02
Re: [PATCH] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
,
Philippe Mathieu-Daudé
,
09:13
[PATCH] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
,
Bin Meng
,
06:36
March 30, 2021
[PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
,
Bin Meng
,
22:18
[PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64
,
Bin Meng
,
22:18
Re: [PATCH V4] target/riscv: Align the data type of reset vector address
,
Alistair Francis
,
14:31
Re: [PATCH V5] target/riscv: Align the data type of reset vector address
,
Alistair Francis
,
12:32
March 29, 2021
[PATCH 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot
,
Bin Meng
,
13:08
[PATCH 7/8] hw/riscv: Use macros for BIOS image names
,
Bin Meng
,
13:08
[PATCH 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage
,
Bin Meng
,
13:08
[PATCH 3/8] hw/riscv: Support the official CLINT DT bindings
,
Bin Meng
,
13:08
[PATCH 5/8] docs/system/riscv: Correct the indentation level of supported devices
,
Bin Meng
,
13:08
[PATCH 4/8] hw/riscv: Support the official PLIC DT bindings
,
Bin Meng
,
13:08
[PATCH 2/8] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
,
Bin Meng
,
13:08
[PATCH 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
,
Bin Meng
,
13:08
Re: [PATCH V5] target/riscv: Align the data type of reset vector address
,
Bin Meng
,
03:16
March 28, 2021
[PATCH V5] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
23:48
[PATCH V4] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
23:39
March 27, 2021
Re: [PATCH V3] target/riscv: Align the data type of reset vector address
,
Alistair Francis
,
20:47
March 26, 2021
Re: [PATCH 1/2] hw/riscv: sifive_u: Allow passing custom DTB
,
Bin Meng
,
09:30
Re: [PATCH V3] target/riscv: Align the data type of reset vector address
,
Peter Maydell
,
07:12
Re: [PATCH V3] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
06:20
March 25, 2021
Re: [PATCH V3] target/riscv: Align the data type of reset vector address
,
Alistair Francis
,
16:21
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Philippe Mathieu-Daudé
,
14:15
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Michael S. Tsirkin
,
13:03
Re: [PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Richard Henderson
,
13:02
[PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Peter Maydell
,
12:33
Re: [PATCH V3] target/riscv: Align the data type of reset vector address
,
Bin Meng
,
06:20
[PATCH V3] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
05:43
Re: [PATCH V2] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
05:29
[PATCH V2] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
01:53
March 24, 2021
Re: [PATCH] target/riscv: Align the data type of reset vector address
,
Bin Meng
,
23:59
Re: [PATCH] target/riscv: Align the data type of reset vector address
,
Bin Meng
,
23:40
Re: [PATCH] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
23:32
Re: [PATCH] target/riscv: Align the data type of reset vector address
,
Alistair Francis
,
11:02
Re: [PATCH 1/2] hw/riscv: sifive_u: Allow passing custom DTB
,
Bin Meng
,
09:41
March 23, 2021
Re: [RFC PATCH 09/13] blobs: Only install firmware blobs if riscv system targets are built
,
Alistair Francis
,
17:30
[RFC PATCH 09/13] blobs: Only install firmware blobs if riscv system targets are built
,
Philippe Mathieu-Daudé
,
11:52
Re: [PATCH] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Peter Maydell
,
06:55
[PATCH] target/riscv: Align the data type of reset vector address
,
Dylan Jhong
,
05:14
March 22, 2021
Re: [PATCH] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Arnd Bergmann
,
19:31
Re: [PATCH] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Michael S. Tsirkin
,
18:35
Re: [PATCH v2] target/riscv: Prevent lost illegal instruction exceptions
,
Richard Henderson
,
17:57
Re: [PATCH 2/2] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
,
Alistair Francis
,
16:36
[PATCH] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
,
Peter Maydell
,
16:13
Re: [PATCH 2/2] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
,
Alistair Francis
,
11:25
Re: [PATCH v2] target/riscv: Prevent lost illegal instruction exceptions
,
Alistair Francis
,
11:23
Re: [PATCH 1/2] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
,
Alistair Francis
,
11:21
Re: [PATCH v2 1/4] target/riscv: Add Shakti C class CPU
,
Alistair Francis
,
11:20
Re: [ RFC 1/6] target/riscv: Remove privilege v1.9 specific CSR related code
,
Alistair Francis
,
10:55
Re: [PATCH v2] target/riscv: Add proper two-stage lookup exception detection
,
Alistair Francis
,
10:32
Re: [PATCH] hw/riscv: Drop the unused fdt pointer
,
Alistair Francis
,
10:30
[PATCH v2] target/riscv: Prevent lost illegal instruction exceptions
,
Georg Kotheimer
,
08:16
[PATCH 2/2] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
,
Bin Meng
,
03:53
[PATCH 1/2] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
,
Bin Meng
,
03:53
March 21, 2021
Re: [RFC 1/1] target/riscv: add support of RNMI
,
Frank Chang
,
22:04
Re: [RFC 0/1] target/riscv: add RNMI support
,
Frank Chang
,
22:04
[PATCH v2 0/4] Add support for Shakti SoC from IIT-M
,
Vijai Kumar K
,
01:09
[PATCH v2 3/4] hw/char: Add Shakti UART emulation
,
Vijai Kumar K
,
01:09
[PATCH v2 2/4] riscv: Add initial support for Shakti C machine
,
Vijai Kumar K
,
01:09
[PATCH v2 1/4] target/riscv: Add Shakti C class CPU
,
Vijai Kumar K
,
01:09
[PATCH v2 4/4] hw/riscv: Connect Shakti UART to Shakti platform
,
Vijai Kumar K
,
01:09
March 20, 2021
Re: [PATCH 1/3] riscv: Add initial support for Shakti C class
,
Vijai Kumar K
,
05:46
Re: [PATCH 2/3] hw/char: Add Shakti UART emulation
,
Vijai Kumar K
,
05:42
Re: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
,
Vijai Kumar K
,
05:38
[PATCH] hw/riscv: Drop the unused fdt pointer
,
Vijai Kumar K
,
05:35
March 19, 2021
[ RFC 6/6] hw/riscv: virt: DEBUG PATCH to test PMU
,
Atish Patra
,
15:46
[ RFC 3/6] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
15:46
[ RFC 4/6] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
15:46
[ RFC 5/6] hw/riscv: virt: Add PMU device tree node to support SBI PMU extension
,
Atish Patra
,
15:45
[ RFC 2/6] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
15:45
[ RFC 0/6] Improve PMU support
,
Atish Patra
,
15:45
[ RFC 1/6] target/riscv: Remove privilege v1.9 specific CSR related code
,
Atish Patra
,
15:45
Re: [PATCH] target/riscv: Prevent lost illegal instruction exceptions
,
Richard Henderson
,
11:22
Re: [PATCH v2] target/riscv: Add proper two-stage lookup exception detection
,
Alistair Francis
,
10:37
[PATCH v2] target/riscv: Add proper two-stage lookup exception detection
,
Georg Kotheimer
,
10:15
Re: [PATCH] target/riscv: Prevent lost illegal instruction exceptions
,
Alistair Francis
,
09:54
Re: [PATCH] target/riscv: Fix read and write accesses to vsip and vsie
,
Alistair Francis
,
09:53
Re: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
,
Alistair Francis
,
09:49
Re: [PATCH 2/3] hw/char: Add Shakti UART emulation
,
Alistair Francis
,
09:46
Re: [PATCH 1/3] riscv: Add initial support for Shakti C class
,
Alistair Francis
,
09:41
Re: [RFC 0/1] target/riscv: add RNMI support
,
Alistair Francis
,
09:30
Re: [RFC 1/1] target/riscv: add support of RNMI
,
Alistair Francis
,
09:29
Re: [PATCH] target/riscv: Fix read and write accesses to vsip and vsie
,
Alistair Francis
,
09:26
Re: [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum
,
Alistair Francis
,
09:21
Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
,
Alistair Francis
,
09:21
Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates
,
Alistair Francis
,
09:19
Re: [PATCH v4 0/2] hw/riscv: Add fw_cfg support, allow ramfb
,
Alistair Francis
,
09:09
Re: [PATCH] target/riscv: Add proper two-stage lookup exception detection
,
Alistair Francis
,
08:51
March 18, 2021
[PATCH v4 2/2] hw/riscv: allow ramfb on virt
,
Asherah Connor
,
19:51
[PATCH v4 1/2] hw/riscv: Add fw_cfg support to virt
,
Asherah Connor
,
19:51
[PATCH v4 0/2] hw/riscv: Add fw_cfg support, allow ramfb
,
Asherah Connor
,
19:50
Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt
,
Asherah Connor
,
19:24
Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt
,
Alistair Francis
,
17:30
Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt
,
Alistair Francis
,
17:26
Re: [PATCH] target/riscv: Make VSTIP and VSEIP read-only in hip
,
Alistair Francis
,
16:36
Re: [PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
,
Alistair Francis
,
16:35
Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
,
Richard Henderson
,
09:25
March 17, 2021
Re: [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum
,
Bin Meng
,
21:58
Re: [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions
,
Alistair Francis
,
16:41
Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates
,
Richard Henderson
,
15:44
Re: [PATCH] target/riscv: Add proper two-stage lookup exception detection
,
Alistair Francis
,
14:26
Re: [PATCH 0/3] target/riscv: fix PMP permission checking when softmmu's TLB hits
,
Alistair Francis
,
13:49
[PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
,
Alistair Francis
,
13:41
[PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations
,
Alistair Francis
,
13:41
[PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions
,
Alistair Francis
,
13:41
[PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates
,
Alistair Francis
,
13:41
[PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum
,
Alistair Francis
,
13:41
[PATCH v1 0/5] RISC-V: Convert the CSR access functions to use
,
Alistair Francis
,
13:41
March 16, 2021
Re: [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions
,
LIU Zhiwei
,
22:31
Re: [PATCH] target/riscv: Use background registers also for MSTATUS_MPV
,
Alistair Francis
,
16:24
Re: [PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
,
Alistair Francis
,
16:18
Re: [PATCH] target/riscv: Add proper two-stage lookup exception detection
,
Alistair Francis
,
16:16
Re: [PATCH] target/riscv: Make VSTIP and VSEIP read-only in hip
,
Alistair Francis
,
16:06
Re: [PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed
,
Alistair Francis
,
16:04
Re: [PATCH 2/3] target/riscv: add log of PMP permission checking
,
Alistair Francis
,
16:04
Re: [PATCH 1/3] target/riscv: propagate PMP permission to TLB page
,
Alistair Francis
,
16:03
Re: [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions
,
Alistair Francis
,
15:56
Re: [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions
,
Alistair Francis
,
15:46
Re: [PATCH 17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions
,
Alistair Francis
,
12:03
[PATCH] target/riscv: Prevent lost illegal instruction exceptions
,
Georg Kotheimer
,
11:04
Re: [PATCH 15/38] target/riscv: 16-bit Packing Instructions
,
Alistair Francis
,
10:44
Re: [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions
,
Alistair Francis
,
10:42
Re: [PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions
,
Alistair Francis
,
10:39
March 15, 2021
Re: [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions
,
LIU Zhiwei
,
22:40
Re: [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions
,
Alistair Francis
,
17:37
Re: [PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions
,
Alistair Francis
,
17:35
Re: [PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions
,
Alistair Francis
,
17:33
Re: [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions
,
Alistair Francis
,
17:29
Re: [PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions
,
Alistair Francis
,
17:28
Re: [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions
,
Alistair Francis
,
17:27
Re: [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction
,
Alistair Francis
,
17:24
March 14, 2021
[PATCH 1/3] riscv: Add initial support for Shakti C class
,
Vijai Kumar K
,
04:40
[PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
,
Vijai Kumar K
,
04:40
[PATCH 2/3] hw/char: Add Shakti UART emulation
,
Vijai Kumar K
,
04:40
[PATCH 0/3] Add support for Shakti SoC from IIT-M
,
Vijai Kumar K
,
04:40
March 12, 2021
Re: [PATCH v5 5/5] tests/tcg: add HeapInfo checking to semihosting test
,
Alex Bennée
,
09:18
Re: [PATCH v5 5/5] tests/tcg: add HeapInfo checking to semihosting test
,
Peter Maydell
,
06:27
Re: [PATCH v5 5/5] tests/tcg: add HeapInfo checking to semihosting test
,
Alex Bennée
,
06:24
Re: [PATCH v5 5/5] tests/tcg: add HeapInfo checking to semihosting test
,
Peter Maydell
,
05:36
Re: [PATCH v5 3/5] semihosting/arm-compat-semi: don't use SET_ARG to report SYS_HEAPINFO
,
Peter Maydell
,
05:32
[PATCH v5 4/5] linux-user/riscv: initialise the TaskState heap/stack info
,
Alex Bennée
,
05:20
[PATCH v5 3/5] semihosting/arm-compat-semi: don't use SET_ARG to report SYS_HEAPINFO
,
Alex Bennée
,
05:20
[PATCH v5 2/5] semihosting/arm-compat-semi: unify GET/SET_ARG helpers
,
Alex Bennée
,
05:20
[PATCH v5 5/5] tests/tcg: add HeapInfo checking to semihosting test
,
Alex Bennée
,
05:20
[PATCH v5 0/5] semihosting/next (SYS_HEAPINFO)
,
Alex Bennée
,
05:20
[PATCH v5 1/5] semihosting: move semihosting tests to multiarch
,
Alex Bennée
,
05:20
March 11, 2021
Re: [PATCH 3/3] Andes AE350 RISC-V Machine
,
Bin Meng
,
20:08
Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
,
Alistair Francis
,
16:43
Re: [PATCH 3/3] Andes AE350 RISC-V Machine
,
Alistair Francis
,
10:47
Re: [PATCH 1/3] Andes RISC-V PLIC
,
Alistair Francis
,
10:43
[PATCH] target/riscv: Use background registers also for MSTATUS_MPV
,
Georg Kotheimer
,
05:30
[PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
,
Georg Kotheimer
,
05:30
[PATCH] target/riscv: Add proper two-stage lookup exception detection
,
Georg Kotheimer
,
05:29
[PATCH] target/riscv: Make VSTIP and VSEIP read-only in hip
,
Georg Kotheimer
,
04:49
[PATCH] target/riscv: Fix read and write accesses to vsip and vsie
,
Georg Kotheimer
,
04:48
[PATCH] hw/riscv: Fix OT IBEX reset vector
,
Alexander Wagner
,
04:25
Re: [PATCH 1/3] Andes RISC-V PLIC
,
Dylan Jhong
,
01:52
Re: [PATCH 3/3] Andes AE350 RISC-V Machine
,
Dylan Jhong
,
01:51
March 10, 2021
[PULL v2 14/15] semihosting: Move include/hw/semihosting/ -> include/semihosting/
,
Alex Bennée
,
11:00
[PULL v2 08/15] hw/riscv: migrate fdt field to generic MachineState
,
Alex Bennée
,
11:00
Re: [PATCH 00/10] target: Provide target-specific Kconfig
,
Claudio Fontana
,
08:30
Re: [PATCH 1/3] Andes RISC-V PLIC
,
Yixun Lan
,
02:53
Re: [PATCH 3/3] Andes AE350 RISC-V Machine
,
Bin Meng
,
01:15
Re: [PATCH 1/3] Andes RISC-V PLIC
,
Bin Meng
,
01:06
March 09, 2021
[PATCH 3/3] Andes AE350 RISC-V Machine
,
Dylan Jhong
,
22:34
[PATCH 2/3] Andes RISC-V PLMT
,
Dylan Jhong
,
22:34
[PATCH 1/3] Andes RISC-V PLIC
,
Dylan Jhong
,
22:34
[PATCH 0/3] Support Andes AE350 Platform
,
Dylan Jhong
,
22:34
Re: [PATCH 03/38] target/riscv: Fixup saturate subtract function
,
Alistair Francis
,
09:12
Re: [PATCH 02/38] target/riscv: Hoist vector functions
,
Alistair Francis
,
09:11
Re: [PATCH 01/38] target/riscv: implementation-defined constant parameters
,
Alistair Francis
,
09:09
[RFC 1/1] target/riscv: add support of RNMI
,
frank . chang
,
02:29
[RFC 0/1] target/riscv: add RNMI support
,
frank . chang
,
02:29
March 08, 2021
Re: [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work
,
Claudio Fontana
,
09:53
Re: [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
,
Claudio Fontana
,
09:52
Re: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
,
Claudio Fontana
,
09:50
[PULL 17/18] semihosting: Move include/hw/semihosting/ -> include/semihosting/
,
Alex Bennée
,
08:57
[PULL 11/18] hw/riscv: migrate fdt field to generic MachineState
,
Alex Bennée
,
08:51
Re: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
,
David Hildenbrand
,
08:40
Re: [PATCH] target/riscv: fix vs() to return proper error code
,
Alistair Francis
,
08:40
Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
,
Philippe Mathieu-Daudé
,
08:37
Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
,
Claudio Fontana
,
07:17
Re: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
,
Claudio Fontana
,
07:13
March 05, 2021
[PATCH v1 1/3] semihosting: Move include/hw/semihosting/ -> include/semihosting/
,
Alex Bennée
,
08:55
Re: [PATCH 0/2] semihosting: Move it out of hw/
,
Alex Bennée
,
05:13
Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2
,
LIU Zhiwei
,
01:14
March 04, 2021
Re: [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps
,
David Gibson
,
20:07
Re: [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
,
David Gibson
,
20:07
[RFC PATCH v2 8/8] target/arm: Restrict arm_cpu_has_work() to TCG
,
Philippe Mathieu-Daudé
,
17:24
[RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps
,
Philippe Mathieu-Daudé
,
17:24
[RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
,
Philippe Mathieu-Daudé
,
17:24
[RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
,
Philippe Mathieu-Daudé
,
17:24
[RFC PATCH v2 4/8] target/s390x: Move s390_cpu_has_work to excp_helper.c
,
Philippe Mathieu-Daudé
,
17:23
[RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work
,
Philippe Mathieu-Daudé
,
17:23
[RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
,
Philippe Mathieu-Daudé
,
17:23
[RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
,
Philippe Mathieu-Daudé
,
17:23
[RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps
,
Philippe Mathieu-Daudé
,
17:23
Re: [RFC PATCH 6/7] cpu: Move CPUClass::has_work() to TCGCPUOps
,
Philippe Mathieu-Daudé
,
14:46
Re: [PATCH 4/7] target/s390x: Move s390_cpu_has_work to excp_helper.c
,
Thomas Huth
,
01:20
Re: [RFC PATCH 6/7] cpu: Move CPUClass::has_work() to TCGCPUOps
,
Thomas Huth
,
01:16
March 03, 2021
RE: [RFC PATCH 6/7] cpu: Move CPUClass::has_work() to TCGCPUOps
,
Taylor Simpson
,
18:03
Re: [PATCH v3 0/2] hw/riscv: Add fw_cfg support, allow ramfb
,
Alistair Francis
,
17:52
RE: [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
,
Taylor Simpson
,
17:42
Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt
,
Alistair Francis
,
17:34
Re: [PATCH v3 2/2] hw/riscv: allow ramfb on virt
,
Alistair Francis
,
17:31
[PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
,
Philippe Mathieu-Daudé
,
16:48
[PATCH v4 13/28] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:48
[PATCH v4 08/28] cpu: Move CPUClass::vmsd to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:48
[PATCH v4 07/28] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
16:48
Re: [PATCH v3 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine
,
Alistair Francis
,
14:07
Re: [PATCH v3 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
,
Alistair Francis
,
14:06
[PATCH v3 2/7] hw/riscv: migrate fdt field to generic MachineState
,
Alex Bennée
,
12:36
Re: [PATCH v3 17/27] linux-user: Remove dead code
,
Laurent Vivier
,
10:18
Re: [PATCH v3 07/27] cpu: Introduce SysemuCPUOps structure
,
Richard Henderson
,
00:18
March 02, 2021
[PATCH v3 18/27] gdbstub: Remove watchpoint dead code in gdbserver_fork()
,
Philippe Mathieu-Daudé
,
10:00
[PATCH v3 17/27] linux-user: Remove dead code
,
Philippe Mathieu-Daudé
,
10:00
[PATCH v3 16/27] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
,
Philippe Mathieu-Daudé
,
10:00
[PATCH v3 15/27] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
10:00
[PATCH v3 14/27] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
10:00
[PATCH v3 13/27] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
10:00
[PATCH v3 12/27] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 11/27] cpu: Move CPUClass::write_elf* to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 10/27] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 09/27] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 08/27] cpu: Move CPUClass::vmsd to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 07/27] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 06/27] cpu: Directly use get_memory_mapping() fallback handlers in place
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 05/27] cpu: Directly use get_paging_enabled() fallback handlers in place
,
Philippe Mathieu-Daudé
,
09:59
[PATCH v3 04/27] cpu: Directly use cpu_write_elf*() fallback handlers in place
,
Philippe Mathieu-Daudé
,
09:58
[PATCH v3 03/27] cpu: Introduce cpu_virtio_is_big_endian()
,
Philippe Mathieu-Daudé
,
09:58
[PATCH v3 02/27] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
,
Philippe Mathieu-Daudé
,
09:58
[PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Philippe Mathieu-Daudé
,
09:58
[PATCH v3 00/27] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode
,
Philippe Mathieu-Daudé
,
09:58
Re: [PATCH 0/2] semihosting: Move it out of hw/
,
Philippe Mathieu-Daudé
,
09:10
Re: [PATCH v2 16/17] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu
,
Philippe Mathieu-Daudé
,
07:39
Re: [PATCH v2 00/17] cpu: Introduce SysemuCPUOps structure
,
Claudio Fontana
,
07:35
Re: [PATCH v2 16/17] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu
,
Claudio Fontana
,
07:34
[PATCH 7/7] target/arm: Restrict arm_cpu_has_work() to TCG
,
Philippe Mathieu-Daudé
,
05:28
[RFC PATCH 6/7] cpu: Move CPUClass::has_work() to TCGCPUOps
,
Philippe Mathieu-Daudé
,
05:28
[RFC PATCH 5/7] cpu: Declare cpu_has_work() in 'sysemu/tcg.h'
,
Philippe Mathieu-Daudé
,
05:28
[PATCH 4/7] target/s390x: Move s390_cpu_has_work to excp_helper.c
,
Philippe Mathieu-Daudé
,
05:28
[PATCH 3/7] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work
,
Philippe Mathieu-Daudé
,
05:28
[PATCH 2/7] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG
,
Philippe Mathieu-Daudé
,
05:28
[PATCH 1/7] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG
,
Philippe Mathieu-Daudé
,
05:27
[RFC PATCH 0/7] cpu: Move CPUClass::has_work() to TCGCPUOps
,
Philippe Mathieu-Daudé
,
05:27
Re: [RFC PATCH v2 17/17] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
,
Philippe Mathieu-Daudé
,
02:34
March 01, 2021
[RFC PATCH v2 17/17] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
,
Philippe Mathieu-Daudé
,
16:53
[PATCH v2 16/17] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu
,
Philippe Mathieu-Daudé
,
16:53
[PATCH v2 15/17] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:53
[PATCH v2 14/17] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:53
[PATCH v2 13/17] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 12/17] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 11/17] cpu: Move CPUClass::write_elf* to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 10/17] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 09/17] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 08/17] cpu: Move CPUClass::vmsd to SysemuCPUOps
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 07/17] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 06/17] cpu: Directly use get_memory_mapping() fallback handlers in place
,
Philippe Mathieu-Daudé
,
16:52
[PATCH v2 05/17] cpu: Directly use get_paging_enabled() fallback handlers in place
,
Philippe Mathieu-Daudé
,
16:51
[PATCH v2 04/17] cpu: Directly use cpu_write_elf*() fallback handlers in place
,
Philippe Mathieu-Daudé
,
16:51
[PATCH v2 03/17] cpu: Introduce cpu_virtio_is_big_endian()
,
Philippe Mathieu-Daudé
,
16:51
[PATCH v2 02/17] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
,
Philippe Mathieu-Daudé
,
16:51
[PATCH v2 01/17] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
,
Philippe Mathieu-Daudé
,
16:51
[PATCH v2 00/17] cpu: Introduce SysemuCPUOps structure
,
Philippe Mathieu-Daudé
,
16:51
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