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qemu-riscv (date)
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Last Modified: Wed Jul 31 2024 15:17:41 -0400
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July 31, 2024
Re: [PATCH v5 13/13] docs/specs: add riscv-iommu
,
Daniel Henrique Barboza
,
15:17
Re: [PATCH v5 11/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications
,
Daniel Henrique Barboza
,
13:21
Re: [PATCH v5 11/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications
,
Andrew Jones
,
12:51
Re: [PATCH v5 11/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications
,
Daniel Henrique Barboza
,
12:27
Re: [RFC 1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores
,
Daniel Henrique Barboza
,
08:38
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
LIU Zhiwei
,
07:21
Re: [PATCH] roms/opensbi: Update to v1.5
,
Daniel Henrique Barboza
,
06:05
Re: [PATCH] target/riscv: Add asserts for out-of-bound access
,
Peter Maydell
,
05:45
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
Alistair Francis
,
05:38
Re: [PATCH] target/riscv: Add asserts for out-of-bound access
,
Alistair Francis
,
05:35
Re: [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension
,
Alistair Francis
,
05:25
[PATCH] hw/char/riscv_htif: Fix 64-bit var write order in 32-bit system
,
Nikita Novikov
,
05:22
Re: [PATCH v5 02/13] hw/riscv: add riscv-iommu-bits.h
,
Jason Chien
,
03:20
July 30, 2024
[PULL 03/14] tests/tcg: Use --noexecstack with assembler files
,
Alex Bennée
,
12:22
Re: [RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
,
Max Chou
,
11:16
Re: [RFC PATCH v5 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Max Chou
,
10:25
Re: [RFC PATCH v5 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance
,
Max Chou
,
09:31
July 29, 2024
Re: [PATCH] roms/opensbi: Update to v1.5
,
Heinrich Schuchardt
,
22:46
Re: [PATCH v2 03/24] target/riscv: save and restore elp state on priv transitions
,
Deepak Gupta
,
22:33
Re: [PATCH v2 03/24] target/riscv: save and restore elp state on priv transitions
,
Richard Henderson
,
22:03
[PATCH v2 24/24] linux-user/riscv: Adding zicfiss/lp extension in hwprobe syscall
,
Deepak Gupta
,
13:54
[PATCH v2 23/24] linux-user: Add RISC-V zicfilp support in VDSO
,
Deepak Gupta
,
13:54
[PATCH v2 20/24] disas/riscv: enable disassembly for compressed sspush/sspopchk
,
Deepak Gupta
,
13:54
[PATCH v2 22/24] linux-user: permit RISC-V CFI dynamic entry in VDSO
,
Deepak Gupta
,
13:54
[PATCH v2 19/24] disas/riscv: enable disassembly for zicfiss instructions
,
Deepak Gupta
,
13:54
[PATCH v2 21/24] target/riscv: add trace-hooks for each case of sw-check exception
,
Deepak Gupta
,
13:54
[PATCH v2 18/24] linux-user/riscv: setup/teardown zicfiss shadow stack for qemu-user
,
Deepak Gupta
,
13:54
[PATCH v2 16/24] target/riscv: shadow stack mmu index for shadow stack instructions
,
Deepak Gupta
,
13:54
[PATCH v2 17/24] linux-user/syscall: introduce prctl for shadow stack enable/disable
,
Deepak Gupta
,
13:54
[PATCH v2 13/24] target/riscv: implement zicfiss instructions
,
Deepak Gupta
,
13:54
[PATCH v2 15/24] target/riscv: mmu changes for zicfiss shadow stack protection
,
Deepak Gupta
,
13:54
[PATCH v2 14/24] target/riscv: compressed encodings for sspush and sspopchk
,
Deepak Gupta
,
13:54
[PATCH v2 12/24] target/riscv: tb flag for shadow stack instructions
,
Deepak Gupta
,
13:54
[PATCH v2 11/24] target/riscv: introduce ssp and enabling controls for zicfiss
,
Deepak Gupta
,
13:54
[PATCH v2 10/24] target/riscv: Add zicfiss extension
,
Deepak Gupta
,
13:53
[PATCH v2 09/24] linux-user/riscv: implement indirect branch tracking prctls
,
Deepak Gupta
,
13:53
[PATCH v2 08/24] linux-user/syscall: introduce prctl for indirect branch tracking
,
Deepak Gupta
,
13:53
[PATCH v2 07/24] disas/riscv: enabled `lpad` disassembly
,
Deepak Gupta
,
13:53
[PATCH v2 06/24] target/riscv: zicfilp `lpad` impl and branch tracking
,
Deepak Gupta
,
13:53
[PATCH v2 04/24] target/riscv: additional code information for sw check
,
Deepak Gupta
,
13:53
[PATCH v2 05/24] target/riscv: tracking indirect branches (fcfi) for zicfilp
,
Deepak Gupta
,
13:53
[PATCH v2 03/24] target/riscv: save and restore elp state on priv transitions
,
Deepak Gupta
,
13:53
[PATCH v2 01/24] target/riscv: Add zicfilp extension
,
Deepak Gupta
,
13:53
[PATCH v2 02/24] target/riscv: Introduce elp state and enabling controls for zicfilp
,
Deepak Gupta
,
13:53
[PATCH v2 00/24] riscv support for control flow integrity extensions
,
Deepak Gupta
,
13:53
Re: [PATCH 13/14] contrib/plugins: add compat for g_memdup2
,
Philippe Mathieu-Daudé
,
11:16
Re: [PATCH 09/14] tests/tcg: move test plugins into tcg subdir
,
Philippe Mathieu-Daudé
,
11:15
[PATCH 13/14] contrib/plugins: add compat for g_memdup2
,
Alex Bennée
,
10:44
[PATCH 10/14] docs: split TCG plugin usage from devel section
,
Alex Bennée
,
10:44
[PATCH 14/14] plugin/loader: handle basic help query
,
Alex Bennée
,
10:44
[PATCH 11/14] contrib/plugins/cache.c: Remove redundant check of l2_access
,
Alex Bennée
,
10:44
[PATCH 08/14] tests/avocado: remove tcg_plugins virt_mem_icount test
,
Alex Bennée
,
10:44
[PATCH 12/14] contrib/plugins: be more vocal building
,
Alex Bennée
,
10:44
[PATCH 07/14] docs/devel: document how to run individual TCG tests
,
Alex Bennée
,
10:44
[PATCH 09/14] tests/tcg: move test plugins into tcg subdir
,
Alex Bennée
,
10:44
[PATCH 05/14] tests/tcg: update README
,
Alex Bennée
,
10:44
[PATCH 04/14] tests/tcg/loongarch64: Use --no-warn-rwx-segments to link system tests
,
Alex Bennée
,
10:44
[PATCH 06/14] docs/devel: update the testing introduction
,
Alex Bennée
,
10:44
[PATCH 03/14] tests/tcg: Use --noexecstack with assembler files
,
Alex Bennée
,
10:44
[PATCH 01/14] gitlab: record installed packages in /packages.txt in containers
,
Alex Bennée
,
10:44
[PATCH 02/14] gitlab: display /packages.txt in build jobs
,
Alex Bennée
,
10:44
[PATCH 00/14] Various fixes and tweaks for 9.1-rc0/1
,
Alex Bennée
,
10:44
Re: [PATCH] RISC-V: Remove riscv_cpu_claim_interrupts()
,
LIU Zhiwei
,
03:51
RE: [PATCH] RISC-V: Remove riscv_cpu_claim_interrupts()
,
張哲嘉
,
02:08
Re: [PATCH] RISC-V: Remove riscv_cpu_claim_interrupts()
,
LIU Zhiwei
,
01:47
July 27, 2024
Re: [RFC 2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amounts of data.
,
Richard Henderson
,
03:16
Re: [RFC 1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores
,
Richard Henderson
,
03:13
how to start second NUMA node in machine virt
,
yfliu2008
,
00:52
[PATCH] RISC-V: Remove riscv_cpu_claim_interrupts()
,
Alvin Chang
,
00:28
July 26, 2024
Re: [PATCH] target/riscv: Add asserts for out-of-bound access
,
Atish Kumar Patra
,
21:36
Re: [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension
,
Atish Kumar Patra
,
21:33
Re: [PATCH] target/riscv: Add asserts for out-of-bound access
,
Atish Kumar Patra
,
21:26
[PATCH v2 1/1] Add support for generating OpenSBI domains in the device tree
,
Gregor Haas
,
14:43
[PATCH v2 0/1] Add support for generating OpenSBI domains in the device tree
,
Gregor Haas
,
14:43
Re: [PATCH] Add support for generating OpenSBI domains in the device tree
,
Gregor Haas
,
14:35
Re: [PATCH] Add support for generating OpenSBI domains in the device tree
,
Daniel Henrique Barboza
,
13:46
Re: [RFC 0/2] Improve the performance of unit-stride RVV ld/st on
,
Daniel Henrique Barboza
,
08:32
Re: [RFC 2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amounts of data.
,
Daniel Henrique Barboza
,
08:27
Re: [RFC 1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores
,
Daniel Henrique Barboza
,
08:22
Re: [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension
,
Alistair Francis
,
03:42
Re: [PATCH] target/riscv: Add asserts for out-of-bound access
,
Alistair Francis
,
01:12
July 25, 2024
Re: [PATCH-for-9.1] target/riscv: Remove the deprecated 'any' CPU type
,
Alistair Francis
,
23:52
[PATCH] Add support for generating OpenSBI domains in the device tree
,
Gregor Haas
,
21:01
[PATCH 24/24] linux-user/riscv: Adding zicfiss/lp extension in hwprobe syscall
,
Deepak Gupta
,
19:47
[PATCH 23/24] linux-user: Add RISC-V zicfilp support in VDSO
,
Deepak Gupta
,
19:46
[PATCH 22/24] linux-user: permit RISC-V CFI dynamic entry in VDSO
,
Deepak Gupta
,
19:46
[PATCH 21/24] target/riscv: add trace-hooks for each case of sw-check exception
,
Deepak Gupta
,
19:46
[PATCH 20/24] disas/riscv: enable disassembly for compressed sspush/sspopchk
,
Deepak Gupta
,
19:46
[PATCH 19/24] disas/riscv: enable disassembly for zicfiss instructions
,
Deepak Gupta
,
19:46
[PATCH 17/24] linux-user/syscall: introduce prctl for shadow stack enable/disable
,
Deepak Gupta
,
19:46
[PATCH 18/24] linux-user/riscv: setup/teardown zicfiss shadow stack for qemu-user
,
Deepak Gupta
,
19:46
[PATCH 11/24] target/riscv: introduce ssp and enabling controls for zicfiss
,
Deepak Gupta
,
19:46
[PATCH 16/24] target/riscv: shadow stack mmu index for shadow stack instructions
,
Deepak Gupta
,
19:46
[PATCH 15/24] target/riscv: mmu changes for zicfiss shadow stack protection
,
Deepak Gupta
,
19:46
[PATCH 12/24] target/riscv: tb flag for shadow stack instructions
,
Deepak Gupta
,
19:46
[PATCH 06/24] target/riscv: zicfilp `lpad` impl and branch tracking
,
Deepak Gupta
,
19:46
[PATCH 09/24] linux-user/riscv: implement indirect branch tracking prctls
,
Deepak Gupta
,
19:46
[PATCH 13/24] target/riscv: implement zicfiss instructions
,
Deepak Gupta
,
19:46
[PATCH 14/24] target/riscv: compressed encodings for sspush and sspopchk
,
Deepak Gupta
,
19:46
[PATCH 10/24] target/riscv: Add zicfiss extension
,
Deepak Gupta
,
19:46
[PATCH 07/24] disas/riscv: enabled `lpad` disassembly
,
Deepak Gupta
,
19:46
[PATCH 08/24] linux-user/syscall: introduce prctl for indirect branch tracking
,
Deepak Gupta
,
19:46
[PATCH 03/24] target/riscv: save and restore elp state on priv transitions
,
Deepak Gupta
,
19:46
[PATCH 05/24] target/riscv: tracking indirect branches (fcfi) for zicfilp
,
Deepak Gupta
,
19:46
[PATCH 04/24] target/riscv: additional code information for sw check
,
Deepak Gupta
,
19:46
[PATCH 02/24] target/riscv: Introduce elp state and enabling controls for zicfilp
,
Deepak Gupta
,
19:46
[PATCH 01/24] target/riscv: Add zicfilp extension
,
Deepak Gupta
,
19:46
[PATCH 00/24] riscv support for control flow integrity extensions
,
Deepak Gupta
,
19:46
Re: [PATCH v5 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Daniel Henrique Barboza
,
08:57
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
07:42
Re: [PATCH-for-9.1] target/riscv: Remove the deprecated 'any' CPU type
,
Daniel Henrique Barboza
,
07:41
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
07:41
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Jonathan Cameron
,
06:59
Re: [PATCH v6 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
,
Alex Bennée
,
06:27
Re: [PATCH 8/8] qemu-options: Add the description of smp-cache object
,
Markus Armbruster
,
05:07
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Markus Armbruster
,
04:52
Re: [PATCH-for-9.1] target/riscv: Remove the deprecated 'any' CPU type
,
Philippe Mathieu-Daudé
,
03:04
Re: [PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Philippe Mathieu-Daudé
,
03:02
Re: [RFC PATCH v5 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance
,
Richard Henderson
,
02:05
Re: [RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
,
Richard Henderson
,
02:04
Re: [RFC PATCH v5 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Richard Henderson
,
01:51
July 24, 2024
Re: [PATCH v5 13/13] docs/specs: add riscv-iommu
,
Alistair Francis
,
23:42
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
Richard Henderson
,
22:45
Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
,
LIU Zhiwei
,
21:55
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
LIU Zhiwei
,
21:52
Re: [PATCH v5 05/13] hw/riscv: add riscv-iommu-pci reference device
,
Daniel Henrique Barboza
,
17:39
Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
,
Peter Maydell
,
14:22
Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
,
Andrew Jones
,
11:01
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
10:54
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
10:40
Re: [PATCH 8/8] qemu-options: Add the description of smp-cache object
,
Zhao Liu
,
10:05
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
09:47
[PATCH-for-9.1] target/riscv: Remove the deprecated 'any' CPU type
,
Philippe Mathieu-Daudé
,
09:07
Re: [PATCH v5 13/13] docs/specs: add riscv-iommu
,
Daniel Henrique Barboza
,
08:56
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Daniel P . Berrangé
,
08:47
Re: [PATCH 8/8] qemu-options: Add the description of smp-cache object
,
Markus Armbruster
,
08:40
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Markus Armbruster
,
07:38
[PATCH] target/riscv: Add asserts for out-of-bound access
,
Atish Patra
,
04:31
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
LIU Zhiwei
,
02:34
July 23, 2024
Re: [PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Alistair Francis
,
22:44
Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR functions
,
Alistair Francis
,
22:40
Re: [PATCH RFC 4/8] target/riscv: Support generic CSR indirect access
,
Atish Kumar Patra
,
19:31
[PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule
,
Atish Patra
,
19:31
[PATCH v2 08/13] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
,
Atish Patra
,
19:31
[PATCH v2 11/13] target/riscv: Repurpose the implied rule startergy
,
Atish Patra
,
19:31
[PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default
,
Atish Patra
,
19:30
[PATCH v2 06/13] target/riscv: Add select value range check for counter delegation
,
Atish Patra
,
19:30
[PATCH v2 12/13] target/riscv: Add a preferred ISA extension rule
,
Atish Patra
,
19:30
[PATCH v2 09/13] target/riscv: Invoke pmu init after feature enable
,
Atish Patra
,
19:30
[PATCH v2 04/13] target/riscv: Support generic CSR indirect access
,
Atish Patra
,
19:30
[PATCH v2 00/13] Add RISC-V Counter delegation ISA extension support
,
Atish Patra
,
19:30
[PATCH v2 07/13] target/riscv: Add counter delegation/configuration support
,
Atish Patra
,
19:30
[PATCH v2 05/13] target/riscv: Add counter delegation definitions
,
Atish Patra
,
19:30
[PATCH v2 03/13] target/riscv: Enable S*stateen bits for AIA
,
Atish Patra
,
19:30
[PATCH v2 02/13] target/riscv: Decouple AIA processing from xiselect and xireg
,
Atish Patra
,
19:30
[PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension
,
Atish Patra
,
19:30
Re: [PATCH v5 11/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications
,
Jason Chien
,
11:25
Re: [PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic
,
Zhao Liu
,
10:24
[PULL v2 50/61] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Michael S. Tsirkin
,
07:00
[PULL v2 51/61] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Michael S. Tsirkin
,
07:00
Re: [PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic
,
Markus Armbruster
,
06:14
Re: [PATCH] target/riscv: Add a property to set vl to ceil(AVL/2)
,
Frank Chang
,
02:56
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
Richard Henderson
,
01:59
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
LIU Zhiwei
,
01:31
July 22, 2024
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
Alistair Francis
,
23:50
Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
Richard Henderson
,
22:11
[PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
,
LIU Zhiwei
,
21:32
[PATCH] target/riscv: Add a property to set vl to ceil(AVL/2)
,
Jason Chien
,
13:50
Re: [PATCH v3 12/12] target/riscv: Simplify probing in vext_ldff
,
Max Chou
,
12:49
Re: [PATCH 8/8] qemu-options: Add the description of smp-cache object
,
Zhao Liu
,
10:26
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
10:15
Re: [PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic
,
Zhao Liu
,
09:46
Re: [PATCH 8/8] qemu-options: Add the description of smp-cache object
,
Markus Armbruster
,
09:38
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Markus Armbruster
,
09:33
Re: [PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic
,
Markus Armbruster
,
09:25
Re: [PATCH v3 11/12] target/s390x: Use set/clear_helper_retaddr in mem_helper.c
,
Peter Maydell
,
08:16
Re: [PATCH v3 10/12] target/s390x: Use user_or_likely in access_memmove
,
Peter Maydell
,
08:10
Re: [PATCH v3 08/12] target/ppc: Improve helper_dcbz for user-only
,
Peter Maydell
,
08:08
Re: [PATCH v3 03/12] target/arm: Use set/clear_helper_retaddr in SVE and SME helpers
,
Peter Maydell
,
07:56
Re: [PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic
,
Markus Armbruster
,
07:56
[PULL 13/16] target/riscv: Restrict semihosting to TCG
,
Alex Bennée
,
07:14
Re: [RFC PATCH v4 1/2] target/riscv: Add RISC-V CSR qtest support
,
Thomas Huth
,
05:51
Re: [RFC PATCH v4 2/2] tests/qtest: QTest example for RISC-V CSR register
,
Thomas Huth
,
05:47
Re: [PATCH 0/8] Introduce SMP Cache Topology
,
Michael S. Tsirkin
,
03:49
Re: [PATCH 0/8] Introduce SMP Cache Topology
,
Zhao Liu
,
03:18
July 21, 2024
non-SMP multi core usage
,
yfliu2008
,
21:48
usage question
,
yfliu2008
,
20:29
[PULL 52/63] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Michael S. Tsirkin
,
20:19
[PULL 51/63] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Michael S. Tsirkin
,
20:19
[PATCH v3 2/2] target/riscv: Add textra matching condition for the triggers
,
Alvin Chang
,
03:25
[PATCH v3 1/2] target/riscv: Preliminary textra trigger CSR writting support
,
Alvin Chang
,
03:25
[PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR functions
,
Alvin Chang
,
03:25
July 20, 2024
Re: [PATCH v6 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
,
Daniel Henrique Barboza
,
05:24
Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
,
Daniel Henrique Barboza
,
05:24
July 19, 2024
[PATCH v6 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
,
LIU Zhiwei
,
19:18
[PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
,
LIU Zhiwei
,
19:18
[PATCH v6 6/8] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
19:17
[PATCH v6 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
19:17
[PATCH v6 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
19:16
[PATCH v6 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
19:16
[PATCH v6 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
19:15
[PATCH v6 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
19:15
[PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
19:14
Re: [PATCH v2 1/2] target/riscv: Preliminary textra trigger CSR writting support
,
Alistair Francis
,
05:41
Re: [PATCH v5 13/13] docs/specs: add riscv-iommu
,
Alistair Francis
,
05:35
Re: [PATCH v5 12/13] qtest/riscv-iommu-test: add init queues test
,
Alistair Francis
,
05:33
July 18, 2024
Re: [PATCH v5 09/13] hw/riscv/riscv-iommu: add ATS support
,
Alistair Francis
,
23:44
[PATCH v3 12/12] target/riscv: Simplify probing in vext_ldff
,
Richard Henderson
,
21:08
[PATCH v3 11/12] target/s390x: Use set/clear_helper_retaddr in mem_helper.c
,
Richard Henderson
,
21:08
[PATCH v3 10/12] target/s390x: Use user_or_likely in access_memmove
,
Richard Henderson
,
21:08
[PATCH v3 08/12] target/ppc: Improve helper_dcbz for user-only
,
Richard Henderson
,
21:08
[PATCH v3 07/12] target/ppc: Merge helper_{dcbz,dcbzep}
,
Richard Henderson
,
21:08
[PATCH v3 09/12] target/s390x: Use user_or_likely in do_access_memset
,
Richard Henderson
,
21:08
[PATCH v3 06/12] target/ppc: Split out helper_dbczl for 970
,
Richard Henderson
,
21:08
[PATCH v3 05/12] target/ppc: Hoist dcbz_size out of dcbz_common
,
Richard Henderson
,
21:07
[PATCH v3 02/12] target/arm: Use set/clear_helper_retaddr in helper-a64.c
,
Richard Henderson
,
21:07
[PATCH v3 04/12] target/ppc/mem_helper.c: Remove a conditional from dcbz_common()
,
Richard Henderson
,
21:07
[PATCH v3 03/12] target/arm: Use set/clear_helper_retaddr in SVE and SME helpers
,
Richard Henderson
,
21:07
[PATCH v3 01/12] accel/tcg: Move {set, clear}_helper_retaddr to cpu_ldst.h
,
Richard Henderson
,
21:07
[PATCH v3 00/12] Fixes for user-only munmap races
,
Richard Henderson
,
21:07
Re: [PATCH v2] target: riscv: Add Svvptc extension support
,
Andrew Jones
,
13:43
Re: [PATCH 06/15] tests/plugins: use qemu_plugin_outs for inline stats
,
Pierrick Bouvier
,
12:37
[PATCH v2] target: riscv: Add Svvptc extension support
,
Alexandre Ghiti
,
12:07
Re: [PATCH 06/15] tests/plugins: use qemu_plugin_outs for inline stats
,
Philippe Mathieu-Daudé
,
07:32
Re: [PATCH 01/15] testing: bump to latest libvirt-ci
,
Philippe Mathieu-Daudé
,
07:30
[PATCH 13/15] target/riscv: Restrict semihosting to TCG
,
Alex Bennée
,
05:45
[PATCH 15/15] semihosting: Restrict to TCG
,
Alex Bennée
,
05:45
[PATCH 14/15] target/xtensa: Restrict semihosting to TCG
,
Alex Bennée
,
05:45
[PATCH 10/15] target/mips: Add semihosting stub
,
Alex Bennée
,
05:45
[PATCH 12/15] target/mips: Restrict semihosting to TCG
,
Alex Bennée
,
05:45
[PATCH 08/15] semihosting: Include missing 'gdbstub/syscalls.h' header
,
Alex Bennée
,
05:45
[PATCH 11/15] target/m68k: Restrict semihosting to TCG
,
Alex Bennée
,
05:45
[PATCH 09/15] target/m68k: Add semihosting stub
,
Alex Bennée
,
05:45
[PATCH 06/15] tests/plugins: use qemu_plugin_outs for inline stats
,
Alex Bennée
,
05:45
[PATCH 01/15] testing: bump to latest libvirt-ci
,
Alex Bennée
,
05:45
[PATCH 07/15] plugins/execlog.c: correct dump of registers values
,
Alex Bennée
,
05:45
[PATCH 05/15] plugins: fix mem callback array size
,
Alex Bennée
,
05:45
[PATCH 00/15] Final bits for 9.1-rc0 (docker, plugins, gdbstub, semihosting)
,
Alex Bennée
,
05:45
[PATCH 02/15] tests/avocado: Remove non-working sparc leon3 test
,
Alex Bennée
,
05:45
[PATCH 03/15] gdbstub: Re-factor gdb command extensions
,
Alex Bennée
,
05:45
[PATCH 04/15] plugins/stoptrigger: TCG plugin to stop execution under conditions
,
Alex Bennée
,
05:45
Re: [PATCH v5 05/13] hw/riscv: add riscv-iommu-pci reference device
,
Jason Chien
,
03:07
Re: [PATCH v5 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
,
Alistair Francis
,
00:51
Re: [PATCH v5 05/13] hw/riscv: add riscv-iommu-pci reference device
,
Alistair Francis
,
00:43
Re: [PATCH v5 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Alistair Francis
,
00:37
July 17, 2024
Re: [PATCH v4 0/8] semihosting: Restrict to TCG
,
Alex Bennée
,
14:21
[RFC 2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amounts of data.
,
Paolo Savini
,
11:48
[RFC 1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores
,
Paolo Savini
,
11:48
[RFC 0/2] Improve the performance of unit-stride RVV ld/st on
,
Paolo Savini
,
11:48
[RFC PATCH v5 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance
,
Max Chou
,
09:40
[RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
,
Max Chou
,
09:40
[RFC PATCH v5 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store
,
Max Chou
,
09:40
[RFC PATCH v5 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
,
Max Chou
,
09:39
[RFC PATCH v5 1/5] target/riscv: Set vdata.vm field for vector load/store whole register instructions
,
Max Chou
,
09:39
[RFC PATCH v5 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
,
Max Chou
,
09:39
[PATCH v4 8/8] semihosting: Restrict to TCG
,
Philippe Mathieu-Daudé
,
06:58
[PATCH v4 7/8] target/xtensa: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
06:58
[PATCH v4 6/8] target/riscv: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
06:58
[PATCH v4 5/8] target/mips: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
06:57
[PATCH v4 4/8] target/m68k: Restrict semihosting to TCG
,
Philippe Mathieu-Daudé
,
06:57
[PATCH v4 3/8] target/mips: Add semihosting stub
,
Philippe Mathieu-Daudé
,
06:57
[PATCH v4 2/8] target/m68k: Add semihosting stub
,
Philippe Mathieu-Daudé
,
06:57
[PATCH v4 1/8] semihosting: Include missing 'gdbstub/syscalls.h' header
,
Philippe Mathieu-Daudé
,
06:57
[PATCH v4 0/8] semihosting: Restrict to TCG
,
Philippe Mathieu-Daudé
,
06:57
July 16, 2024
[PATCH v4 8/9] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
10:44
[PATCH v4 9/9] tests/acpi: Add expected ACPI AML files for RISC-V
,
Sunil V L
,
10:44
[PATCH v4 7/9] tests/acpi: Add empty ACPI data files for RISC-V
,
Sunil V L
,
10:44
[PATCH v4 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path
,
Sunil V L
,
10:43
[PATCH v4 5/9] tests/acpi: update expected DSDT blob for aarch64 and microvm
,
Sunil V L
,
10:43
[PATCH v4 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64
,
Sunil V L
,
10:43
[PATCH v4 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge
,
Sunil V L
,
10:43
[PATCH v4 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Sunil V L
,
10:43
[PATCH v4 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Sunil V L
,
10:43
[PATCH v4 0/9] RISC-V: ACPI: Namespace updates
,
Sunil V L
,
10:43
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Igor Mammedov
,
10:34
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Igor Mammedov
,
10:28
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Sunil V L
,
08:26
Re: [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Sunil V L
,
08:14
Re: [PATCH v3 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge
,
Igor Mammedov
,
06:33
Re: [PATCH v3 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Igor Mammedov
,
06:28
Re: [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Igor Mammedov
,
06:24
Re: [PATCH] roms/opensbi: Update to v1.5
,
Daniel Henrique Barboza
,
05:04
July 15, 2024
Re: [PATCH] roms/opensbi: Update to v1.5
,
Alistair Francis
,
19:29
Re: [PATCH v2] hw/riscv/virt.c: re-insert and deprecate 'riscv, delegate'
,
Alistair Francis
,
19:13
Re: [PATCH v2 13/13] target/riscv: Simplify probing in vext_ldff
,
Richard Henderson
,
17:43
[PATCH] roms/opensbi: Update to v1.5
,
Daniel Henrique Barboza
,
13:15
[PATCH v3 9/9] tests/acpi: Add expected ACPI AML files for RISC-V
,
Sunil V L
,
13:12
[PATCH v3 8/9] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
13:12
[PATCH v3 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path
,
Sunil V L
,
13:12
[PATCH v3 7/9] tests/acpi: Add empty ACPI data files for RISC-V
,
Sunil V L
,
13:12
[PATCH v3 5/9] tests/acpi: update expected DSDT blob for aarch64 and microvm
,
Sunil V L
,
13:12
[PATCH v3 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge
,
Sunil V L
,
13:11
[PATCH v3 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64
,
Sunil V L
,
13:11
[PATCH v3 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Sunil V L
,
13:11
[PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Sunil V L
,
13:11
[PATCH v3 0/9] RISC-V: ACPI: Namespace updates
,
Sunil V L
,
13:11
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Igor Mammedov
,
08:44
[PATCH v8 8/8] hw/riscv/virt: Add IOPMP support
,
Ethan Chen
,
06:15
[PATCH v8 7/8] hw/misc/riscv_iopmp: Add DMA operation with IOPMP support API
,
Ethan Chen
,
06:14
[PATCH v8 6/8] hw/misc/riscv_iopmp: Add API to configure RISCV CPU IOPMP support
,
Ethan Chen
,
06:14
[PATCH v8 5/8] hw/misc/riscv_iopmp: Add API to set up IOPMP protection for system memory
,
Ethan Chen
,
06:13
[PATCH v8 4/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
,
Ethan Chen
,
05:58
[PATCH v8 3/8] target/riscv: Add support for IOPMP
,
Ethan Chen
,
05:57
[PATCH v8 2/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size
,
Ethan Chen
,
05:57
[PATCH v8 0/8] Support RISC-V IOPMP
,
Ethan Chen
,
05:57
[PATCH v8 1/8] memory: Introduce memory region fetch operation
,
Ethan Chen
,
05:57
[PATCH v2] hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'
,
Daniel Henrique Barboza
,
05:05
Re: [PATCH] hw/riscv/virt.c: re-insert and deprecate 'riscv, delegate'
,
Daniel Henrique Barboza
,
04:54
Re: [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
,
Daniel Henrique Barboza
,
04:42
Re: [PATCH v2 13/13] target/riscv: Simplify probing in vext_ldff
,
Max Chou
,
03:07
July 14, 2024
Re: [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
21:33
Re: [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
21:31
Re: [PATCH v8 00/13] Add RISC-V ISA extension smcntrpmf support
,
Alistair Francis
,
21:02
Re: [PATCH v8 13/13] target/riscv: Expose the Smcntrpmf config
,
Alistair Francis
,
20:54
Re: [PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is available
,
Alistair Francis
,
20:49
[PATCH qemu v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
~yuming
,
20:47
Re: [PATCH v8 05/13] target/riscv: Add cycle & instret privilege mode filtering support
,
Alistair Francis
,
20:47
Re: [PATCH v8 03/13] target/riscv: Add cycle & instret privilege mode filtering properties
,
Alistair Francis
,
20:43
Re: [PATCH] hw/riscv/virt.c: re-insert and deprecate 'riscv, delegate'
,
Alistair Francis
,
20:36
Re: [PATCH] hw/riscv/virt.c: re-insert and deprecate 'riscv, delegate'
,
Alistair Francis
,
19:03
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Michael S. Tsirkin
,
03:46
July 13, 2024
Re: [PATCH] hw/riscv/virt.c: re-insert and deprecate 'riscv, delegate'
,
Conor Dooley
,
14:57
[PATCH] hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'
,
Daniel Henrique Barboza
,
13:43
July 12, 2024
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Igor Mammedov
,
09:50
Re: [PATCH v2 10/13] target/s390x: Use user_or_likely in do_access_memset
,
Peter Maydell
,
09:02
Re: [PATCH v2 04/13] target/arm: Use set/clear_helper_retaddr in SVE and SME helpers
,
Peter Maydell
,
09:01
Re: [PATCH v2 03/13] target/arm: Use set/clear_helper_retaddr in helper-a64.c
,
Peter Maydell
,
08:54
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Daniel P . Berrangé
,
08:51
Re: [PATCH v2 02/13] target/arm: Use cpu_env in cpu_untagged_addr
,
Peter Maydell
,
08:49
Re: [PATCH v2 01/13] accel/tcg: Move {set, clear}_helper_retaddr to cpu_ldst.h
,
Peter Maydell
,
08:48
Re: [PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Igor Mammedov
,
08:43
Re: [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Daniel Henrique Barboza
,
05:57
Re: [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
,
Daniel Henrique Barboza
,
05:52
Re: [PATCH v4 04/11] disas/riscv: Support zcmop disassemble
,
Jim Shu
,
05:08
Re: [PATCH v4 03/11] target/riscv: Add zcmop extension
,
Jim Shu
,
05:07
Re: [PATCH v4 02/11] disas/riscv: Support zimop disassemble
,
Jim Shu
,
05:07
Re: [PATCH v4 01/11] target/riscv: Add zimop extension
,
Jim Shu
,
05:05
[PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
Yu-Ming Chang
,
03:19
Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
Alistair Francis
,
01:20
Re: [PATCH v2 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Sunil V L
,
01:08
July 11, 2024
Re: [RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support
,
Alistair Francis
,
22:03
Re: [RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension
,
Alistair Francis
,
21:44
Re: [RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension
,
Alistair Francis
,
21:43
Re: [RFC PATCH 04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
,
Alistair Francis
,
21:41
Re: [RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs
,
Alistair Francis
,
21:39
Re: [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Alistair Francis
,
21:34
[PATCH v8 13/13] target/riscv: Expose the Smcntrpmf config
,
Atish Patra
,
18:31
[PATCH v8 12/13] target/riscv: Do not setup pmu timer if OF is disabled
,
Atish Patra
,
18:31
[PATCH v8 11/13] target/riscv: More accurately model priv mode filtering.
,
Atish Patra
,
18:31
[PATCH v8 10/13] target/riscv: Start counters from both mhpmcounter and mcountinhibit
,
Atish Patra
,
18:31
[PATCH v8 09/13] target/riscv: Enforce WARL behavior for scounteren/hcounteren
,
Atish Patra
,
18:31
[PATCH v8 08/13] target/riscv: Save counter values during countinhibit update
,
Atish Patra
,
18:31
[PATCH v8 05/13] target/riscv: Add cycle & instret privilege mode filtering support
,
Atish Patra
,
18:31
[PATCH v8 07/13] target/riscv: Implement privilege mode filtering for cycle/instret
,
Atish Patra
,
18:31
[PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is available
,
Atish Patra
,
18:31
[PATCH v8 04/13] target/riscv: Add cycle & instret privilege mode filtering definitions
,
Atish Patra
,
18:31
[PATCH v8 03/13] target/riscv: Add cycle & instret privilege mode filtering properties
,
Atish Patra
,
18:31
[PATCH v8 02/13] target/riscv: Fix the predicate functions for mhpmeventhX CSRs
,
Atish Patra
,
18:31
[PATCH v8 00/13] Add RISC-V ISA extension smcntrpmf support
,
Atish Patra
,
18:31
[PATCH v8 01/13] target/riscv: Combine set_mode and set_virt functions.
,
Atish Patra
,
18:31
Re: [PATCH v2 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Michael S. Tsirkin
,
10:41
Re: [PATCH v2 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path
,
Igor Mammedov
,
09:53
Re: [PATCH v2 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64
,
Igor Mammedov
,
09:53
Re: [PATCH v2 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge
,
Igor Mammedov
,
09:43
Re: [PATCH v2 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Igor Mammedov
,
09:25
Re: [PATCH v2 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Igor Mammedov
,
09:21
Re: [PATCH v2 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Igor Mammedov
,
09:17
July 10, 2024
Re: [PATCH v2 09/13] target/ppc: Improve helper_dcbz for user-only
,
Richard Henderson
,
10:42
Re: [PATCH v2 08/13] target/ppc: Merge helper_{dcbz,dcbzep}
,
Richard Henderson
,
10:41
Re: [PATCH v2 06/13] target/ppc: Hoist dcbz_size out of dcbz_common
,
Richard Henderson
,
10:37
Re: [PATCH v2 09/13] target/ppc: Improve helper_dcbz for user-only
,
BALATON Zoltan
,
08:26
Re: [PATCH v2 08/13] target/ppc: Merge helper_{dcbz,dcbzep}
,
BALATON Zoltan
,
08:21
Re: [PATCH v2 07/13] target/ppc: Split out helper_dbczl for 970
,
BALATON Zoltan
,
08:18
Re: [PATCH v2 06/13] target/ppc: Hoist dcbz_size out of dcbz_common
,
BALATON Zoltan
,
08:11
[PATCH v2 2/2] target/riscv: Add textra matching condition for the triggers
,
Alvin Chang
,
06:00
[PATCH v2 1/2] target/riscv: Preliminary textra trigger CSR writting support
,
Alvin Chang
,
06:00
[PATCH v2 0/2] RISC-V: Add preliminary textra trigger CSR functions
,
Alvin Chang
,
06:00
Re: [PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support
,
Atish Kumar Patra
,
03:38
Re: [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties
,
Atish Kumar Patra
,
03:04
Re: [PATCH v2 13/13] target/riscv: Simplify probing in vext_ldff
,
Alistair Francis
,
00:09
July 09, 2024
[PATCH v2 12/13] target/s390x: Use set/clear_helper_retaddr in mem_helper.c
,
Richard Henderson
,
23:28
[PATCH v2 13/13] target/riscv: Simplify probing in vext_ldff
,
Richard Henderson
,
23:28
[PATCH v2 11/13] target/s390x: Use user_or_likely in access_memmove
,
Richard Henderson
,
23:28
[PATCH v2 09/13] target/ppc: Improve helper_dcbz for user-only
,
Richard Henderson
,
23:28
[PATCH v2 08/13] target/ppc: Merge helper_{dcbz,dcbzep}
,
Richard Henderson
,
23:28
[PATCH v2 10/13] target/s390x: Use user_or_likely in do_access_memset
,
Richard Henderson
,
23:28
[PATCH v2 04/13] target/arm: Use set/clear_helper_retaddr in SVE and SME helpers
,
Richard Henderson
,
23:28
[PATCH v2 07/13] target/ppc: Split out helper_dbczl for 970
,
Richard Henderson
,
23:28
[PATCH v2 05/13] target/ppc/mem_helper.c: Remove a conditional from dcbz_common()
,
Richard Henderson
,
23:28
[PATCH v2 06/13] target/ppc: Hoist dcbz_size out of dcbz_common
,
Richard Henderson
,
23:28
[PATCH v2 03/13] target/arm: Use set/clear_helper_retaddr in helper-a64.c
,
Richard Henderson
,
23:28
[PATCH v2 02/13] target/arm: Use cpu_env in cpu_untagged_addr
,
Richard Henderson
,
23:28
[PATCH v2 01/13] accel/tcg: Move {set, clear}_helper_retaddr to cpu_ldst.h
,
Richard Henderson
,
23:28
[PATCH v2 00/13] Fixes for user-only munmap races
,
Richard Henderson
,
23:28
[PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
22:30
[PATCH v5 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
22:29
[PATCH v5 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
22:29
[PATCH v5 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
22:28
[PATCH v5 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
22:28
[PATCH v5 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
22:27
[PATCH v5 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
22:27
[PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
22:26
Re: [PATCH v4 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
21:40
Re: [PATCH v4 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
Alistair Francis
,
21:40
Re: [PATCH v4 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
Alistair Francis
,
21:33
Re: [PATCH v4 7/7] tests/avocado: Add an avocado test for riscv64
,
Alistair Francis
,
21:31
Re: [PATCH 2/2] target/riscv: Add textra matching condition for the triggers
,
Alistair Francis
,
21:30
Re: [PATCH 1/2] target/riscv: Preliminary textra trigger CSR writting support
,
Alistair Francis
,
21:23
Re: [PATCH v2 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path
,
Alistair Francis
,
20:55
Re: [PATCH] target/riscv/kvm: update KVM regs to Linux 6.10-rc5
,
Alistair Francis
,
20:51
Re: [PATCH] target/riscv/kvm: update KVM regs to Linux 6.10-rc5
,
Alistair Francis
,
20:26
Re: [PATCH 0/2] target/arm: Fix unwind from dc zva and FEAT_MOPS
,
Richard Henderson
,
12:17
[PATCH v4 11/11] disas/riscv: Support zabha disassemble
,
LIU Zhiwei
,
07:44
[PATCH v4 10/11] target/riscv: Expose zabha extension as a cpu property
,
LIU Zhiwei
,
07:44
[PATCH v4 09/11] target/riscv: Add amocas.[b|h] for Zabha
,
LIU Zhiwei
,
07:43
[PATCH v4 08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
,
LIU Zhiwei
,
07:42
[PATCH v4 07/11] target/riscv: Add AMO instructions for Zabha
,
LIU Zhiwei
,
07:42
[PATCH v4 06/11] target/riscv: Move gen_amo before implement Zabha
,
LIU Zhiwei
,
07:41
[PATCH v4 05/11] target/riscv: Support Zama16b extension
,
LIU Zhiwei
,
07:41
[PATCH v4 04/11] disas/riscv: Support zcmop disassemble
,
LIU Zhiwei
,
07:41
[PATCH v4 03/11] target/riscv: Add zcmop extension
,
LIU Zhiwei
,
07:40
[PATCH v4 02/11] disas/riscv: Support zimop disassemble
,
LIU Zhiwei
,
07:40
[PATCH v4 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
LIU Zhiwei
,
07:40
[PATCH v4 01/11] target/riscv: Add zimop extension
,
LIU Zhiwei
,
07:39
Re: [PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
05:57
[PATCH] target/riscv/kvm: update KVM regs to Linux 6.10-rc5
,
Daniel Henrique Barboza
,
04:54
July 08, 2024
[PATCH v5 13/13] docs/specs: add riscv-iommu
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 12/13] qtest/riscv-iommu-test: add init queues test
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 11/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 06/13] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 09/13] hw/riscv/riscv-iommu: add ATS support
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 10/13] hw/riscv/riscv-iommu: add DBG support
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 03/13] hw/riscv: add RISC-V IOMMU base emulation
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 07/13] test/qtest: add riscv-iommu-pci tests
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 05/13] hw/riscv: add riscv-iommu-pci reference device
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 04/13] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 01/13] exec/memtxattr: add process identifier to the transaction attributes
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 02/13] hw/riscv: add riscv-iommu-bits.h
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 00/13] riscv: QEMU RISC-V IOMMU Support
,
Daniel Henrique Barboza
,
13:35
Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events
,
Philippe Mathieu-Daudé
,
09:42
[PATCH v4 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
09:22
[PATCH v4 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
09:21
[PATCH v4 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
09:21
[PATCH v4 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
09:20
[PATCH v4 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
09:20
[PATCH v4 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
09:19
[PATCH v4 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
09:19
[PATCH v4 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
09:18
[PATCH v2 9/9] tests/acpi: Add expected ACPI AML files for RISC-V
,
Sunil V L
,
07:48
[PATCH v2 8/9] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
,
Sunil V L
,
07:48
[PATCH v2 5/9] tests/acpi: update expected DSDT blob for aarch64 and microvm
,
Sunil V L
,
07:48
[PATCH v2 7/9] tests/acpi: Add empty ACPI data files for RISC-V
,
Sunil V L
,
07:48
[PATCH v2 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path
,
Sunil V L
,
07:48
[PATCH v2 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge
,
Sunil V L
,
07:48
[PATCH v2 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64
,
Sunil V L
,
07:48
[PATCH v2 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
,
Sunil V L
,
07:48
[PATCH v2 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
,
Sunil V L
,
07:48
[PATCH v2 0/9] RISC-V: ACPI: Namespace updates
,
Sunil V L
,
07:47
Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events
,
Aleksei Filippov
,
05:46
Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support
,
Alistair Francis
,
00:27
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Sunil V L
,
00:26
Re: [PATCH] target/riscv: Fix the check with vector register multiples of LMUL
,
Alistair Francis
,
00:17
Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
Alistair Francis
,
00:05
July 07, 2024
Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
,
Alistair Francis
,
23:58
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Alistair Francis
,
23:17
Re: [PATCH v3 7/7] tests/avocado: Add an avocado test for riscv64
,
Alistair Francis
,
22:48
Re: [PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
Alistair Francis
,
22:45
Re: [PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
Alistair Francis
,
22:43
Re: [PATCH v2] disas/riscv: Add decode for Zawrs extension
,
Alistair Francis
,
22:37
Re: [PATCH v2] disas/riscv: Add decode for Zawrs extension
,
Alistair Francis
,
22:19
Re: [PATCH v4 00/14] riscv: QEMU RISC-V IOMMU Support
,
Alistair Francis
,
22:18
Re: [PATCH] hw/intc: sifive_plic: Fix heap-buffer-overflow in SiFive PLIC read operation
,
Alistair Francis
,
22:18
Re: [PATCH v3 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
Alistair Francis
,
22:01
July 05, 2024
Re: [PATCH v4 00/14] riscv: QEMU RISC-V IOMMU Support
,
Daniel Henrique Barboza
,
17:25
Re: [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation
,
Daniel Henrique Barboza
,
17:12
[PATCH v2] disas/riscv: Add decode for Zawrs extension
,
Rob Bradford
,
12:53
July 04, 2024
Re: [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation
,
Jason Chien
,
10:20
Re: [PATCH] hw/intc: sifive_plic: Fix heap-buffer-overflow in SiFive PLIC read operation
,
Peter Maydell
,
05:32
[PATCH 2/2] target/riscv: Add textra matching condition for the triggers
,
Alvin Chang
,
00:02
[PATCH 1/2] target/riscv: Preliminary textra trigger CSR writting support
,
Alvin Chang
,
00:02
[PATCH 0/2] RISC-V: Add preliminary textra trigger CSR functions
,
Alvin Chang
,
00:02
July 03, 2024
[PATCH 5/8] i386/cpu: Support thread and module level cache topology
,
Zhao Liu
,
23:01
[PATCH 8/8] qemu-options: Add the description of smp-cache object
,
Zhao Liu
,
23:01
[PATCH 7/8] i386/pc: Support cache topology in -machine for PC machine
,
Zhao Liu
,
23:01
[PATCH 4/8] hw/core: Check smp cache topology support for machine
,
Zhao Liu
,
23:01
[PATCH 6/8] i386/cpu: Update cache topology with machine's configuration
,
Zhao Liu
,
23:01
[PATCH 3/8] hw/core: Add smp cache topology for machine
,
Zhao Liu
,
23:00
[PATCH 2/8] qapi/qom: Introduce smp-cache object
,
Zhao Liu
,
23:00
[PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic
,
Zhao Liu
,
23:00
[PATCH 0/8] Introduce SMP Cache Topology
,
Zhao Liu
,
23:00
[PATCH] hw/intc: sifive_plic: Fix heap-buffer-overflow in SiFive PLIC read operation
,
Zheyu Ma
,
18:03
Re: [PATCH v4 02/14] hw/riscv: add riscv-iommu-bits.h
,
Daniel Henrique Barboza
,
16:21
Re: [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
Richard Henderson
,
12:49
Re: [PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
Richard Henderson
,
12:48
Re: [PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
11:07
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Sunil V L
,
10:57
[PATCH v3 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
10:55
[PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
10:54
[PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
10:53
[PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
10:53
[PATCH v3 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
10:52
[PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
10:52
[PATCH v3 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
10:51
[PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
10:51
Re: [PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Philippe Mathieu-Daudé
,
09:08
[PATCH v2 7/7] tests/avocado: Add an avocado test for riscv64
,
LIU Zhiwei
,
08:40
[PATCH v2 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
,
LIU Zhiwei
,
08:39
[PATCH v2 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
,
LIU Zhiwei
,
08:39
[PATCH v2 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
08:38
[PATCH v2 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
08:38
[PATCH v2 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
LIU Zhiwei
,
08:37
[PATCH v2 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
LIU Zhiwei
,
08:37
[PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
,
LIU Zhiwei
,
08:36
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Sunil V L
,
06:23
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
LIU Zhiwei
,
04:48
[RFC PATCH v4 2/2] tests/qtest: QTest example for RISC-V CSR register
,
Ivan Klokov
,
04:20
[RFC PATCH v4 1/2] target/riscv: Add RISC-V CSR qtest support
,
Ivan Klokov
,
04:20
[RFC PATCH v4 0/2] Support RISC-V CSR read/write in Qtest environment
,
Ivan Klokov
,
04:20
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Philippe Mathieu-Daudé
,
03:33
July 02, 2024
Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
LIU Zhiwei
,
22:48
Re: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Alistair Francis
,
22:36
Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
,
Alistair Francis
,
22:33
Re: [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
,
Alistair Francis
,
22:28
Re: [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
,
Alistair Francis
,
22:27
Re: [PATCH] disas/riscv: Add decode for Zawrs extension
,
Alistair Francis
,
22:21
Re: [PATCH] disas/riscv: Add decode for Zawrs extension
,
Alistair Francis
,
22:13
Re: [PATCH v3 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
Alistair Francis
,
22:11
Re: [PATCH v7 07/11] target/riscv: Save counter values during countinhibit update
,
Alistair Francis
,
22:04
Re: [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties
,
Alistair Francis
,
22:03
[PATCH v3 05/11] target/riscv: Support Zama16b extension
,
LIU Zhiwei
,
21:56
[PATCH v3 11/11] disas/riscv: Support zabha disassemble
,
LIU Zhiwei
,
21:54
[PATCH v3 10/11] target/riscv: Expose zabha extension as a cpu property
,
LIU Zhiwei
,
21:53
[PATCH v3 09/11] target/riscv: Add amocas.[b|h] for Zabha
,
LIU Zhiwei
,
21:53
[PATCH v3 08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
,
LIU Zhiwei
,
21:52
[PATCH v3 07/11] target/riscv: Add AMO instructions for Zabha
,
LIU Zhiwei
,
21:51
[PATCH v3 06/11] target/riscv: Move gen_amo before implement Zabha
,
LIU Zhiwei
,
21:51
[PATCH v3 04/11] disas/riscv: Support zcmop disassemble
,
LIU Zhiwei
,
21:50
[PATCH v3 03/11] target/riscv: Add zcmop extension
,
LIU Zhiwei
,
21:49
[PATCH v3 02/11] disas/riscv: Support zimop disassemble
,
LIU Zhiwei
,
21:49
[PATCH v3 01/11] target/riscv: Add zimop extension
,
LIU Zhiwei
,
21:48
[PATCH v3 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
LIU Zhiwei
,
21:48
Re: [PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret
,
Alistair Francis
,
21:25
Re: [PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support
,
Alistair Francis
,
21:19
Re: [PATCH v7 04/11] target/riscv: Add cycle & instret privilege mode filtering definitions
,
Alistair Francis
,
21:13
Re: [PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.
,
Alistair Francis
,
21:07
Re: [PATCH v2 10/11] target/riscv: Enable zabha for max cpu
,
Alistair Francis
,
20:29
Re: [PATCH v2 05/11] target/riscv: Support Zama16b extension
,
Alistair Francis
,
20:12
Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
,
Alistair Francis
,
19:59
Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame
,
Alistair Francis
,
19:57
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Alistair Francis
,
19:56
Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
,
Richard Henderson
,
19:08
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Richard Henderson
,
19:04
Re: [PATCH v2 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha
,
Deepak Gupta
,
18:34
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Daniel Henrique Barboza
,
18:17
Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame
,
Daniel Henrique Barboza
,
18:16
Re: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
,
Daniel Henrique Barboza
,
18:16
Re: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame
,
Philippe Mathieu-Daudé
,
15:58
Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
,
Philippe Mathieu-Daudé
,
15:56
Re: [PATCH 0/3] util: Add cpuinfo support for riscv
,
Richard Henderson
,
12:26
Re: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
,
Philippe Mathieu-Daudé
,
10:19
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Jonathan Cameron
,
10:02
Re: [PATCH v4 06/16] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Sunil V L
,
04:33
Re: [PATCH v4 06/16] tests/qtest/bios-tables-test.c: Add support for arch in path
,
Igor Mammedov
,
04:30
July 01, 2024
Re: [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
LIU Zhiwei
,
21:50
Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
,
Michael S. Tsirkin
,
17:04
Re: [PATCH v7 11/11] target/riscv: Do not setup pmu timer if OF is disabled
,
Daniel Henrique Barboza
,
15:39
Re: [PATCH v7 10/11] target/riscv: More accurately model priv mode filtering.
,
Daniel Henrique Barboza
,
15:38
Re: [PATCH v7 09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit
,
Daniel Henrique Barboza
,
15:37
Re: [PATCH v7 07/11] target/riscv: Save counter values during countinhibit update
,
Daniel Henrique Barboza
,
15:34
Re: [PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret
,
Daniel Henrique Barboza
,
15:30
Re: [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties
,
Daniel Henrique Barboza
,
15:10
Re: [PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.
,
Daniel Henrique Barboza
,
14:21
Re: [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
,
Philippe Mathieu-Daudé
,
11:10
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