[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [avr-gcc-list] ATmega16 PWM
From: |
Thomas D. Dean |
Subject: |
Re: [avr-gcc-list] ATmega16 PWM |
Date: |
Sun, 15 Jul 2007 22:57:30 -0700 (PDT) |
Thanks for the replies.
I understand basic PWM.
For example, if I modulate the PWM with 600Hz, and use, say, 8
samples per cycle of the 600Hz, I change the PW every 1.67ms.
To recover the original modulation, I think I need something like 10
samples of the highest modulation frequency. So, for 600Hz, and
changing OCR 8 times per cycle, and the 2x Nyquist, I need 9600Hz
PWM frequency.
An ATmega16 w/ 8e6 clk, I can get fast PWM frequency of 31kHz, I can
get a max modulation frequency of 1937Hz.
Is this true?
What about a complex waveform, f1+f2+...fn, fn<1937. I need to look
at the fft.
I did some measurements and washed it thru scilab, below.
tomdean
Fast PWM Mode
Clock 8.00e+06
PWM frequency as measured vs the book value.
cs Measured Book Diff
-- --------- --------- ----
1 3.205e+04 3.125e+04 2.6%
2 4.010e+03 3.906e+03 2.7%
3 1.000e+03 9.766e+02 2.4%
4 5.008e+02 4.883e+02 2.6%
5 2.506e+02 2.441e+02 2.6%
6 1.252e+02 1.221e+02 2.6%
7 3.129e+01 3.052e+01 2.5%
Measured Cycles
Pdif = measured period-(uptime+downtime)
DCycle = duty cycle, 100*uptime/period
Derr = duty cycle error, 100*(dc-ocr/256)/(ocr/256)
OCR Up Time Down Time Pdif DCycle DErr
--- --------- --------- ----- ------ -----
20 4.000e-06 2.712e-05 -0.13% 12.8% 2.70%
40 7.920e-06 2.325e-05 0.03% 25.4% 1.67%
60 1.181e-05 1.936e-05 0.03% 37.9% 1.07%
80 1.570e-05 1.544e-05 -0.06% 50.4% 0.77%
A0 1.953e-05 1.158e-05 -0.16% 62.7% 0.28%
C0 2.347e-05 7.820e-06 0.42% 75.3% 0.43%
E0 2.740e-05 3.760e-06 0.00% 87.9% 0.50%
Phase Correct PWM Mode
Clock 8.00e+06
PWM frequency as measured vs the book value.
cs Measured Book Diff
-- --------- --------- ----
1 1.610e+04 1.562e+04 3.0%
2 2.010e+03 1.953e+03 2.9%
3 5.030e+02 4.883e+02 3.0%
4 2.515e+02 2.441e+02 3.0%
5 1.256e+02 1.221e+02 2.9%
6 6.285e+01 6.104e+01 3.0%
7 1.572e+01 1.526e+01 3.0%
Measured Cycles
Pdif = measured period-(uptime+downtime)
DCycle = duty cycle, 100*uptime/period
Derr = duty cycle error, 100*(dc-ocr/256)/(ocr/256)
OCR Up Time Down Time Pdif DCycle DErr
--- --------- --------- ----- ------ -----
20 7.800e-06 5.430e-05 0.03% 12.6% 0.52%
40 1.560e-05 4.648e-05 0.00% 25.1% 0.52%
60 2.337e-05 3.872e-05 0.02% 37.6% 0.39%
80 3.116e-05 3.091e-05 -0.02% 50.2% 0.39%
A0 3.896e-05 2.314e-05 0.03% 62.8% 0.41%
C0 4.676e-05 1.532e-05 0.00% 75.3% 0.43%
E0 5.451e-05 7.590e-06 0.03% 87.8% 0.35%
Modulate the PWM with 600Hz and 8 samples per cycle.
Assuming a 16-bit counter.
n OCR @t
-- --- --------
1 80 0.00e+00
2 ad 1.67e-03
3 c0 3.33e-03
4 ad 5.00e-03
5 80 6.67e-03
6 52 8.33e-03
7 40 1.00e-02
8 52 1.17e-02
The interval between changes in OCR is
uint8_t num_points = 8;
uint16_t delay_count = 0x3415;
uint8_t ocr_value[8] = { 0x80, 0xad, 0xc0, 0xad, 0x80, 0x52, 0x40, 0x52 };
- [avr-gcc-list] ATmega16 PWM, Thomas D. Dean, 2007/07/15
- Re: [avr-gcc-list] ATmega16 PWM, Joerg Wunsch, 2007/07/16
- Re: [avr-gcc-list] ATmega16 PWM,
Thomas D. Dean <=
- Re: [avr-gcc-list] ATmega16 PWM, Per-Tore Aasestrand, 2007/07/26
- Re: [avr-gcc-list] ATmega16 PWM, Joerg Wunsch, 2007/07/26
- Re: [avr-gcc-list] ATmega16 PWM, Per-Tore Aasestrand, 2007/07/26
- Re: [avr-gcc-list] ATmega16 PWM, Joerg Wunsch, 2007/07/26
- Re: [avr-gcc-list] ATmega16 PWM, Thomas D. Dean, 2007/07/26
- Re: [avr-gcc-list] ATmega16 PWM, David VanHorn, 2007/07/26
- Re: [avr-gcc-list] ATmega16 PWM, Per-Tore Aasestrand, 2007/07/28
- Message not available
- Message not available
- Re: [avr-gcc-list] ATmega16 PWM, Per-Tore Aasestrand, 2007/07/27