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[avr-libc-commit] [2406] bug #39783: add CRC definitions and update PR d
|
From: |
Pitchumani |
|
Subject: |
[avr-libc-commit] [2406] bug #39783: add CRC definitions and update PR definitions for xmega 64/128/ 192 and 256 d3 devices |
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Date: |
Mon, 17 Mar 2014 13:33:36 +0000 |
Revision: 2406
http://svn.sv.gnu.org/viewvc/?view=rev&root=avr-libc&revision=2406
Author: pitchumani
Date: 2014-03-17 13:33:35 +0000 (Mon, 17 Mar 2014)
Log Message:
-----------
bug #39783: add CRC definitions and update PR definitions for xmega 64/128/192
and 256 d3 devices
Ticket Links:
------------
http://savannah.gnu.org/bugs/?39783
Modified Paths:
--------------
trunk/avr-libc/include/avr/iox128d3.h
trunk/avr-libc/include/avr/iox192d3.h
trunk/avr-libc/include/avr/iox256d3.h
trunk/avr-libc/include/avr/iox64d3.h
trunk/avr-libc/include/avr/power.h
Added Paths:
-----------
trunk/avr-libc/ChangeLog
Added: trunk/avr-libc/ChangeLog
===================================================================
--- trunk/avr-libc/ChangeLog (rev 0)
+++ trunk/avr-libc/ChangeLog 2014-03-17 13:33:35 UTC (rev 2406)
@@ -0,0 +1,12 @@
+2014-03-17 Pitchumani Sivanupandi <address@hidden>
+
+ * include/avr/iox64d3.h (PR_struct): Remove PRPB.
+ (CRC_struct): Add CRC definitions.
+ Remove incorrect PR definitions.
+ * include/avr/iox128d3.h: Same.
+ * include/avr/iox192d3.h: Same.
+ * include/avr/iox256d3.h (PR_struct): Add power reduction definitions.
+ (CRC_struct): Add CRC definitions.
+ Add PR and CRC macro definitions.
+ * include/avr/power.h: Add power reduction macro docs and update power
+ reduction macro definitions for xmega64/128/192/256 D3 devices.
Modified: trunk/avr-libc/include/avr/iox128d3.h
===================================================================
--- trunk/avr-libc/include/avr/iox128d3.h 2014-03-17 11:46:39 UTC (rev
2405)
+++ trunk/avr-libc/include/avr/iox128d3.h 2014-03-17 13:33:35 UTC (rev
2406)
@@ -174,7 +174,7 @@
{
register8_t PRGEN; /* General Power Reduction */
register8_t PRPA; /* Power Reduction Port A */
- register8_t PRPB; /* Power Reduction Port B */
+ register8_t reserved_0x02;
register8_t PRPC; /* Power Reduction Port C */
register8_t PRPD; /* Power Reduction Port D */
register8_t PRPE; /* Power Reduction Port E */
@@ -416,6 +416,46 @@
/*
--------------------------------------------------------------------------
+CRC - Cyclic Redundancy Checker
+--------------------------------------------------------------------------
+*/
+
+/* Cyclic Redundancy Checker */
+typedef struct CRC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t DATAIN; /* Data Input */
+ register8_t CHECKSUM0; /* Checksum byte 0 */
+ register8_t CHECKSUM1; /* Checksum byte 1 */
+ register8_t CHECKSUM2; /* Checksum byte 2 */
+ register8_t CHECKSUM3; /* Checksum byte 3 */
+} CRC_t;
+
+/* Reset */
+typedef enum CRC_RESET_enum
+{
+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros
*/
+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
+} CRC_RESET_t;
+
+/* Input Source */
+typedef enum CRC_SOURCE_enum
+{
+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
+} CRC_SOURCE_t;
+
+
+/*
+--------------------------------------------------------------------------
EVSYS - Event System
--------------------------------------------------------------------------
*/
@@ -2180,6 +2220,7 @@
#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
@@ -2309,7 +2350,6 @@
/* PR - Power Reduction */
#define PR_PRGEN _SFR_MEM8(0x0070)
#define PR_PRPA _SFR_MEM8(0x0071)
-#define PR_PRPB _SFR_MEM8(0x0072)
#define PR_PRPC _SFR_MEM8(0x0073)
#define PR_PRPD _SFR_MEM8(0x0074)
#define PR_PRPE _SFR_MEM8(0x0075)
@@ -2345,6 +2385,15 @@
#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+/* CRC - Cyclic Redundancy Checker */
+#define CRC_CTRL _SFR_MEM8(0x00D0)
+#define CRC_STATUS _SFR_MEM8(0x00D1)
+#define CRC_DATAIN _SFR_MEM8(0x00D3)
+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
+
/* EVSYS - Event System */
#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
@@ -2901,59 +2950,31 @@
/* PR.PRGEN bit masks and bit positions */
-#define PR_AES_bm 0x10 /* AES bit mask. */
-#define PR_AES_bp 4 /* AES bit position. */
-
-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
-#define PR_EBI_bp 3 /* External Bus Interface bit position. */
-
#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
#define PR_RTC_bp 2 /* Real-time Counter bit position. */
#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
#define PR_EVSYS_bp 1 /* Event System bit position. */
-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
-#define PR_DMA_bp 0 /* DMA-Controller bit position. */
-
-
/* PR.PRPA bit masks and bit positions */
-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
-#define PR_DAC_bp 2 /* Port A DAC bit position. */
-
#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
#define PR_ADC_bp 1 /* Port A ADC bit position. */
#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
-
-/* PR.PRPB bit masks and bit positions */
-/* PR_DAC_bm Predefined. */
-/* PR_DAC_bp Predefined. */
-
-/* PR_ADC_bm Predefined. */
-/* PR_ADC_bp Predefined. */
-
-/* PR_AC_bm Predefined. */
-/* PR_AC_bp Predefined. */
-
-
/* PR.PRPC bit masks and bit positions */
#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
-#define PR_USART1_bp 5 /* Port C USART1 bit position. */
-
#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
#define PR_USART0_bp 4 /* Port C USART0 bit position. */
#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
#define PR_SPI_bp 3 /* Port C SPI bit position. */
-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */
+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */
#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
@@ -2961,76 +2982,33 @@
#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
-
/* PR.PRPD bit masks and bit positions */
-/* PR_TWI_bm Predefined. */
-/* PR_TWI_bp Predefined. */
-
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
/* PR_SPI_bm Predefined. */
/* PR_SPI_bp Predefined. */
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* PR.PRPE bit masks and bit positions */
/* PR_TWI_bm Predefined. */
/* PR_TWI_bp Predefined. */
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
-/* PR_SPI_bm Predefined. */
-/* PR_SPI_bp Predefined. */
-
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* PR.PRPF bit masks and bit positions */
-/* PR_TWI_bm Predefined. */
-/* PR_TWI_bp Predefined. */
-
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
-/* PR_SPI_bm Predefined. */
-/* PR_SPI_bp Predefined. */
-
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* SLEEP - Sleep Controller */
/* SLEEP.CTRL bit masks and bit positions */
#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
@@ -3311,6 +3289,37 @@
#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+/* CRC - Cyclic Redundancy Checker */
+/* CRC.CTRL bit masks and bit positions */
+#define CRC_RESET_gm 0xC0 /* Reset group mask. */
+#define CRC_RESET_gp 6 /* Reset group position. */
+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
+
+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
+
+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
+#define CRC_SOURCE_gp 0 /* Input Source group position. */
+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
+
+/* CRC.STATUS bit masks and bit positions */
+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
+#define CRC_ZERO_bp 1 /* Zero detection bit position. */
+
+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
+#define CRC_BUSY_bp 0 /* Busy bit position. */
+
+
/* EVSYS - Event System */
/* EVSYS.CH0MUX bit masks and bit positions */
#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
Modified: trunk/avr-libc/include/avr/iox192d3.h
===================================================================
--- trunk/avr-libc/include/avr/iox192d3.h 2014-03-17 11:46:39 UTC (rev
2405)
+++ trunk/avr-libc/include/avr/iox192d3.h 2014-03-17 13:33:35 UTC (rev
2406)
@@ -174,7 +174,7 @@
{
register8_t PRGEN; /* General Power Reduction */
register8_t PRPA; /* Power Reduction Port A */
- register8_t PRPB; /* Power Reduction Port B */
+ register8_t reserved_0x02;
register8_t PRPC; /* Power Reduction Port C */
register8_t PRPD; /* Power Reduction Port D */
register8_t PRPE; /* Power Reduction Port E */
@@ -416,6 +416,46 @@
/*
--------------------------------------------------------------------------
+CRC - Cyclic Redundancy Checker
+--------------------------------------------------------------------------
+*/
+
+/* Cyclic Redundancy Checker */
+typedef struct CRC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t DATAIN; /* Data Input */
+ register8_t CHECKSUM0; /* Checksum byte 0 */
+ register8_t CHECKSUM1; /* Checksum byte 1 */
+ register8_t CHECKSUM2; /* Checksum byte 2 */
+ register8_t CHECKSUM3; /* Checksum byte 3 */
+} CRC_t;
+
+/* Reset */
+typedef enum CRC_RESET_enum
+{
+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros
*/
+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
+} CRC_RESET_t;
+
+/* Input Source */
+typedef enum CRC_SOURCE_enum
+{
+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
+} CRC_SOURCE_t;
+
+
+/*
+--------------------------------------------------------------------------
EVSYS - Event System
--------------------------------------------------------------------------
*/
@@ -2180,6 +2220,7 @@
#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
@@ -2309,7 +2350,6 @@
/* PR - Power Reduction */
#define PR_PRGEN _SFR_MEM8(0x0070)
#define PR_PRPA _SFR_MEM8(0x0071)
-#define PR_PRPB _SFR_MEM8(0x0072)
#define PR_PRPC _SFR_MEM8(0x0073)
#define PR_PRPD _SFR_MEM8(0x0074)
#define PR_PRPE _SFR_MEM8(0x0075)
@@ -2345,6 +2385,15 @@
#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+/* CRC - Cyclic Redundancy Checker */
+#define CRC_CTRL _SFR_MEM8(0x00D0)
+#define CRC_STATUS _SFR_MEM8(0x00D1)
+#define CRC_DATAIN _SFR_MEM8(0x00D3)
+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
+
/* EVSYS - Event System */
#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
@@ -2901,59 +2950,31 @@
/* PR.PRGEN bit masks and bit positions */
-#define PR_AES_bm 0x10 /* AES bit mask. */
-#define PR_AES_bp 4 /* AES bit position. */
-
-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
-#define PR_EBI_bp 3 /* External Bus Interface bit position. */
-
#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
#define PR_RTC_bp 2 /* Real-time Counter bit position. */
#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
#define PR_EVSYS_bp 1 /* Event System bit position. */
-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
-#define PR_DMA_bp 0 /* DMA-Controller bit position. */
-
-
/* PR.PRPA bit masks and bit positions */
-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
-#define PR_DAC_bp 2 /* Port A DAC bit position. */
-
#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
#define PR_ADC_bp 1 /* Port A ADC bit position. */
#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
-
-/* PR.PRPB bit masks and bit positions */
-/* PR_DAC_bm Predefined. */
-/* PR_DAC_bp Predefined. */
-
-/* PR_ADC_bm Predefined. */
-/* PR_ADC_bp Predefined. */
-
-/* PR_AC_bm Predefined. */
-/* PR_AC_bp Predefined. */
-
-
/* PR.PRPC bit masks and bit positions */
#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
-#define PR_USART1_bp 5 /* Port C USART1 bit position. */
-
#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
#define PR_USART0_bp 4 /* Port C USART0 bit position. */
#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
#define PR_SPI_bp 3 /* Port C SPI bit position. */
-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */
+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */
#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
@@ -2961,76 +2982,33 @@
#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
-
/* PR.PRPD bit masks and bit positions */
-/* PR_TWI_bm Predefined. */
-/* PR_TWI_bp Predefined. */
-
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
/* PR_SPI_bm Predefined. */
/* PR_SPI_bp Predefined. */
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* PR.PRPE bit masks and bit positions */
/* PR_TWI_bm Predefined. */
/* PR_TWI_bp Predefined. */
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
-/* PR_SPI_bm Predefined. */
-/* PR_SPI_bp Predefined. */
-
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* PR.PRPF bit masks and bit positions */
-/* PR_TWI_bm Predefined. */
-/* PR_TWI_bp Predefined. */
-
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
-/* PR_SPI_bm Predefined. */
-/* PR_SPI_bp Predefined. */
-
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* SLEEP - Sleep Controller */
/* SLEEP.CTRL bit masks and bit positions */
#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
@@ -3311,6 +3289,37 @@
#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+/* CRC - Cyclic Redundancy Checker */
+/* CRC.CTRL bit masks and bit positions */
+#define CRC_RESET_gm 0xC0 /* Reset group mask. */
+#define CRC_RESET_gp 6 /* Reset group position. */
+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
+
+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
+
+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
+#define CRC_SOURCE_gp 0 /* Input Source group position. */
+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
+
+/* CRC.STATUS bit masks and bit positions */
+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
+#define CRC_ZERO_bp 1 /* Zero detection bit position. */
+
+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
+#define CRC_BUSY_bp 0 /* Busy bit position. */
+
+
/* EVSYS - Event System */
/* EVSYS.CH0MUX bit masks and bit positions */
#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
Modified: trunk/avr-libc/include/avr/iox256d3.h
===================================================================
--- trunk/avr-libc/include/avr/iox256d3.h 2014-03-17 11:46:39 UTC (rev
2405)
+++ trunk/avr-libc/include/avr/iox256d3.h 2014-03-17 13:33:35 UTC (rev
2406)
@@ -163,6 +163,19 @@
register8_t RTCCTRL; /* RTC Control Register */
} CLK_t;
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+ register8_t PRGEN; /* General Power Reduction */
+ register8_t PRPA; /* Power Reduction Port A */
+ register8_t reserved_0x02;
+ register8_t PRPC; /* Power Reduction Port C */
+ register8_t PRPD; /* Power Reduction Port D */
+ register8_t PRPE; /* Power Reduction Port E */
+ register8_t PRPF; /* Power Reduction Port F */
+} PR_t;
+
/* System Clock Selection */
typedef enum CLK_SCLKSEL_enum
{
@@ -398,6 +411,46 @@
/*
--------------------------------------------------------------------------
+CRC - Cyclic Redundancy Checker
+--------------------------------------------------------------------------
+*/
+
+/* Cyclic Redundancy Checker */
+typedef struct CRC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t DATAIN; /* Data Input */
+ register8_t CHECKSUM0; /* Checksum byte 0 */
+ register8_t CHECKSUM1; /* Checksum byte 1 */
+ register8_t CHECKSUM2; /* Checksum byte 2 */
+ register8_t CHECKSUM3; /* Checksum byte 3 */
+} CRC_t;
+
+/* Reset */
+typedef enum CRC_RESET_enum
+{
+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros
*/
+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
+} CRC_RESET_t;
+
+/* Input Source */
+typedef enum CRC_SOURCE_enum
+{
+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
+} CRC_SOURCE_t;
+
+
+/*
+--------------------------------------------------------------------------
EVSYS - Event System
--------------------------------------------------------------------------
*/
@@ -2144,6 +2197,7 @@
#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
@@ -2270,6 +2324,14 @@
#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
+/* PR - Power Reduction */
+#define PR_PRGEN _SFR_MEM8(0x0070)
+#define PR_PRPA _SFR_MEM8(0x0071)
+#define PR_PRPC _SFR_MEM8(0x0073)
+#define PR_PRPD _SFR_MEM8(0x0074)
+#define PR_PRPE _SFR_MEM8(0x0075)
+#define PR_PRPF _SFR_MEM8(0x0076)
+
/* RST - Reset Controller */
#define RST_STATUS _SFR_MEM8(0x0078)
#define RST_CTRL _SFR_MEM8(0x0079)
@@ -2300,6 +2362,15 @@
#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+/* CRC - Cyclic Redundancy Checker */
+#define CRC_CTRL _SFR_MEM8(0x00D0)
+#define CRC_STATUS _SFR_MEM8(0x00D1)
+#define CRC_DATAIN _SFR_MEM8(0x00D3)
+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
+
/* EVSYS - Event System */
#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
@@ -2855,7 +2926,66 @@
#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
+/* PR.PRGEN bit masks and bit positions */
+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
+#define PR_RTC_bp 2 /* Real-time Counter bit position. */
+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
+#define PR_EVSYS_bp 1 /* Event System bit position. */
+
+/* PR.PRPA bit masks and bit positions */
+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
+#define PR_ADC_bp 1 /* Port A ADC bit position. */
+
+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
+
+/* PR.PRPC bit masks and bit positions */
+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
+
+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
+#define PR_USART0_bp 4 /* Port C USART0 bit position. */
+
+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
+#define PR_SPI_bp 3 /* Port C SPI bit position. */
+
+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */
+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */
+
+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
+
+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
+
+/* PR.PRPD bit masks and bit positions */
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+/* PR.PRPE bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+/* PR.PRPF bit masks and bit positions */
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
/* SLEEP - Sleep Controller */
/* SLEEP.CTRL bit masks and bit positions */
#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
@@ -3136,6 +3266,37 @@
#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+/* CRC - Cyclic Redundancy Checker */
+/* CRC.CTRL bit masks and bit positions */
+#define CRC_RESET_gm 0xC0 /* Reset group mask. */
+#define CRC_RESET_gp 6 /* Reset group position. */
+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
+
+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
+
+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
+#define CRC_SOURCE_gp 0 /* Input Source group position. */
+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
+
+/* CRC.STATUS bit masks and bit positions */
+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
+#define CRC_ZERO_bp 1 /* Zero detection bit position. */
+
+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
+#define CRC_BUSY_bp 0 /* Busy bit position. */
+
+
/* EVSYS - Event System */
/* EVSYS.CH0MUX bit masks and bit positions */
#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
Modified: trunk/avr-libc/include/avr/iox64d3.h
===================================================================
--- trunk/avr-libc/include/avr/iox64d3.h 2014-03-17 11:46:39 UTC (rev
2405)
+++ trunk/avr-libc/include/avr/iox64d3.h 2014-03-17 13:33:35 UTC (rev
2406)
@@ -174,7 +174,7 @@
{
register8_t PRGEN; /* General Power Reduction */
register8_t PRPA; /* Power Reduction Port A */
- register8_t PRPB; /* Power Reduction Port B */
+ register8_t reserved_0x02;
register8_t PRPC; /* Power Reduction Port C */
register8_t PRPD; /* Power Reduction Port D */
register8_t PRPE; /* Power Reduction Port E */
@@ -416,6 +416,46 @@
/*
--------------------------------------------------------------------------
+CRC - Cyclic Redundancy Checker
+--------------------------------------------------------------------------
+*/
+
+/* Cyclic Redundancy Checker */
+typedef struct CRC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t DATAIN; /* Data Input */
+ register8_t CHECKSUM0; /* Checksum byte 0 */
+ register8_t CHECKSUM1; /* Checksum byte 1 */
+ register8_t CHECKSUM2; /* Checksum byte 2 */
+ register8_t CHECKSUM3; /* Checksum byte 3 */
+} CRC_t;
+
+/* Reset */
+typedef enum CRC_RESET_enum
+{
+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros
*/
+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
+} CRC_RESET_t;
+
+/* Input Source */
+typedef enum CRC_SOURCE_enum
+{
+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
+} CRC_SOURCE_t;
+
+
+/*
+--------------------------------------------------------------------------
EVSYS - Event System
--------------------------------------------------------------------------
*/
@@ -2180,6 +2220,7 @@
#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
@@ -2311,7 +2352,6 @@
/* PR - Power Reduction */
#define PR_PRGEN _SFR_MEM8(0x0070)
#define PR_PRPA _SFR_MEM8(0x0071)
-#define PR_PRPB _SFR_MEM8(0x0072)
#define PR_PRPC _SFR_MEM8(0x0073)
#define PR_PRPD _SFR_MEM8(0x0074)
#define PR_PRPE _SFR_MEM8(0x0075)
@@ -2347,6 +2387,15 @@
#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+/* CRC - Cyclic Redundancy Checker */
+#define CRC_CTRL _SFR_MEM8(0x00D0)
+#define CRC_STATUS _SFR_MEM8(0x00D1)
+#define CRC_DATAIN _SFR_MEM8(0x00D3)
+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
+
/* EVSYS - Event System */
#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
@@ -2915,59 +2964,31 @@
/* PR.PRGEN bit masks and bit positions */
-#define PR_AES_bm 0x10 /* AES bit mask. */
-#define PR_AES_bp 4 /* AES bit position. */
-
-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
-#define PR_EBI_bp 3 /* External Bus Interface bit position. */
-
#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
#define PR_RTC_bp 2 /* Real-time Counter bit position. */
#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
#define PR_EVSYS_bp 1 /* Event System bit position. */
-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
-#define PR_DMA_bp 0 /* DMA-Controller bit position. */
-
-
/* PR.PRPA bit masks and bit positions */
-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
-#define PR_DAC_bp 2 /* Port A DAC bit position. */
-
#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
#define PR_ADC_bp 1 /* Port A ADC bit position. */
#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
-
-/* PR.PRPB bit masks and bit positions */
-/* PR_DAC_bm Predefined. */
-/* PR_DAC_bp Predefined. */
-
-/* PR_ADC_bm Predefined. */
-/* PR_ADC_bp Predefined. */
-
-/* PR_AC_bm Predefined. */
-/* PR_AC_bp Predefined. */
-
-
/* PR.PRPC bit masks and bit positions */
#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
-#define PR_USART1_bp 5 /* Port C USART1 bit position. */
-
#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
#define PR_USART0_bp 4 /* Port C USART0 bit position. */
#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
#define PR_SPI_bp 3 /* Port C SPI bit position. */
-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */
+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */
#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
@@ -2975,76 +2996,33 @@
#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
-
/* PR.PRPD bit masks and bit positions */
-/* PR_TWI_bm Predefined. */
-/* PR_TWI_bp Predefined. */
-
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
/* PR_SPI_bm Predefined. */
/* PR_SPI_bp Predefined. */
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* PR.PRPE bit masks and bit positions */
/* PR_TWI_bm Predefined. */
/* PR_TWI_bp Predefined. */
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
-/* PR_SPI_bm Predefined. */
-/* PR_SPI_bp Predefined. */
-
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* PR.PRPF bit masks and bit positions */
-/* PR_TWI_bm Predefined. */
-/* PR_TWI_bp Predefined. */
-
-/* PR_USART1_bm Predefined. */
-/* PR_USART1_bp Predefined. */
-
/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */
-/* PR_SPI_bm Predefined. */
-/* PR_SPI_bp Predefined. */
-
-/* PR_HIRES_bm Predefined. */
-/* PR_HIRES_bp Predefined. */
-
-/* PR_TC1_bm Predefined. */
-/* PR_TC1_bp Predefined. */
-
/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */
-
/* SLEEP - Sleep Controller */
/* SLEEP.CTRL bit masks and bit positions */
#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
@@ -3325,6 +3303,37 @@
#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+/* CRC - Cyclic Redundancy Checker */
+/* CRC.CTRL bit masks and bit positions */
+#define CRC_RESET_gm 0xC0 /* Reset group mask. */
+#define CRC_RESET_gp 6 /* Reset group position. */
+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
+
+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
+
+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
+#define CRC_SOURCE_gp 0 /* Input Source group position. */
+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
+
+/* CRC.STATUS bit masks and bit positions */
+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
+#define CRC_ZERO_bp 1 /* Zero detection bit position. */
+
+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
+#define CRC_BUSY_bp 0 /* Busy bit position. */
+
+
/* EVSYS - Event System */
/* EVSYS.CH0MUX bit masks and bit positions */
#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
Modified: trunk/avr-libc/include/avr/power.h
===================================================================
--- trunk/avr-libc/include/avr/power.h 2014-03-17 11:46:39 UTC (rev 2405)
+++ trunk/avr-libc/include/avr/power.h 2014-03-17 13:33:35 UTC (rev 2406)
@@ -81,6 +81,18 @@
</tr>
<tr>
+ <td>power_aca_disable()</td>
+ <td>Disable the Analog Comparator on PortA.</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_aca_enable()</td>
+ <td>Enable the Analog Comparator on PortA.</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
<td>power_adc_enable()</td>
<td>Enable the Analog to Digital Converter module.</td>
<td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560,
ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1,
AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81,
ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A,
ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A,
ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P,
ATmega644, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84,
ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861,
ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2,
ATmega644RFR2</td>
@@ -93,6 +105,42 @@
</tr>
<tr>
+ <td>power_adca_disable()</td>
+ <td>Disable the Analog to Digital Converter module on PortA</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_adca_enable()</td>
+ <td>Enable the Analog to Digital Converter module on PortA</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_evsys_disable()</td>
+ <td>Disable the EVSYS module</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_evsys_enable()</td>
+ <td>Enable the EVSYS module</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresc_disable()</td>
+ <td>Disable the HIRES module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresc_enable()</td>
+ <td>Enable the HIRES module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
<td>power_lcd_enable()</td>
<td>Enable the LCD module.</td>
<td>ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A,
ATmega649, ATmega6490</td>
@@ -213,6 +261,18 @@
</tr>
<tr>
+ <td>power_rtc_disable()</td>
+ <td>Disable the RTC module</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_rtc_enable()</td>
+ <td>Enable the RTC module</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
<td>power_spi_enable()</td>
<td>Enable the Serial Peripheral Interface module.</td>
<td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560,
ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1,
AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81,
ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A,
ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A,
ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P,
ATmega644, ATmega48, ATmega88, ATmega168, ATmega256RFR2, ATmega2564RFR2,
ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
@@ -225,6 +285,114 @@
</tr>
<tr>
+ <td>power_spic_disable()</td>
+ <td>Disable the SPI module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_spic_enable()</td>
+ <td>Enable the SPI module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_spid_disable()</td>
+ <td>Disable the SPI module on PortD</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_spid_enable()</td>
+ <td>Enable the SPI module on PortD</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0c_disable()</td>
+ <td>Disable the TC0 module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0c_enable()</td>
+ <td>Enable the TC0 module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0d_disable()</td>
+ <td>Disable the TC0 module on PortD</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0d_enable()</td>
+ <td>Enable the TC0 module on PortD</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0e_disable()</td>
+ <td>Disable the TC0 module on PortE</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0e_enable()</td>
+ <td>Enable the TC0 module on PortE</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0f_disable()</td>
+ <td>Disable the TC0 module on PortF</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0f_enable()</td>
+ <td>Enable the TC0 module on PortF</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1c_disable()</td>
+ <td>Disable the TC1 module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1c_enable()</td>
+ <td>Enable the TC1 module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_twic_disable()</td>
+ <td>Disable the Two Wire Interface module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_twic_enable()</td>
+ <td>Enable the Two Wire Interface module on PortC</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_twie_disable()</td>
+ <td>Disable the Two Wire Interface module on PortE</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
+ <td>power_twie_enable()</td>
+ <td>Enable the Two Wire Interface module on PortE</td>
+ <td>ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega256D3</td>
+ </tr>
+
+ <tr>
<td>power_timer0_enable()</td>
<td>Enable the Timer 0 module.</td>
<td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560,
ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1,
AT90PWM216, AT90PWM316, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, ATmega165,
ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645,
ATmega6450, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88,
ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45,
ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2,
ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
@@ -369,6 +537,54 @@
</tr>
<tr>
+ <td>power_usartc0_disable()</td>
+ <td> Disable the USART0 module on PortC</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usartc0_enable()</td>
+ <td> Enable the USART0 module on PortC</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usartd0_disable()</td>
+ <td> Disable the USART0 module on PortD</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usartd0_enable()</td>
+ <td> Enable the USART0 module on PortD</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usarte0_disable()</td>
+ <td> Disable the USART0 module on PortE</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usarte0_enable()</td>
+ <td> Enable the USART0 module on PortE</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usartf0_disable()</td>
+ <td> Disable the USART0 module on PortF</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usartf0_enable()</td>
+ <td> Enable the USART0 module on PortF</td>
+ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
<td>power_usb_enable()</td>
<td>Enable the USB module.</td>
<td>AT90USB646, AT90USB647, AT90USB1286, AT90USB1287</td>
@@ -407,13 +623,13 @@
<tr>
<td>power_all_enable()</td>
<td>Enable all modules.</td>
- <td>ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3,
ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B,
ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATmega640,
ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646,
AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3,
AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325,
ATmega325A, ATmega3250, ATmega325A, ATmega645, ATmega6450, ATmega169,
ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649,
ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88,
ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45,
ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2,
ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
+ <td>ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3,
ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B,
ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3,
ATxmega256D3, ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560,
ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1,
AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165,
ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega325A, ATmega645,
ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290,
ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644,
ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84,
ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861,
ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2,
ATmega644RFR2</td>
</tr>
<tr>
<td>power_all_disable()</td>
<td>Disable all modules.</td>
- <td>ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3,
ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B,
ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3,ATxmega192D3, ATmega640,
ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646,
AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3,
AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325,
ATmega325A, ATmega3250, ATmega325A, ATmega645, ATmega6450, ATmega169,
ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649,
ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88,
ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45,
ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega256RFR2, ATmega2564RFR2,
ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2, ATmega644RFR2</td>
+ <td>ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3,
ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B,
ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3,
ATxmega256D3, ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560,
ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1,
AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165,
ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega325A, ATmega645,
ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290,
ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644,
ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84,
ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861,
ATmega256RFR2, ATmega2564RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega64RFR2,
ATmega644RFR2</td>
</tr>
</table>
</center>
@@ -482,6 +698,79 @@
} while(0)
#endif
+#if defined(__AVR_ATxmega64D3__) \
+|| defined(__AVR_ATxmega128D3__) \
+|| defined(__AVR_ATxmega192D3__) \
+|| defined(__AVR_ATxmega256D3__)
+
+#define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
+#define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
+
+#define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
+#define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
+
+#define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
+#define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
+
+#define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
+#define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
+
+#define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
+#define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
+#define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
+#define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
+
+#define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
+#define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
+#define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
+#define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
+#define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
+#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
+#define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
+#define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
+
+#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
+#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
+#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
+#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
+
+#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
+#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
+
+#define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
+#define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
+
+#define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
+#define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
+#define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
+#define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
+#define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
+#define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
+#define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
+#define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
+
+#define power_all_enable() \
+do { \
+ PR_PRGEN &= (uint8_t)~(PR_RTC_bm|PR_EVSYS_bm); \
+ PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \
+ PR_PRPC &=
(uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
+ PR_PRPD &= (uint8_t)~(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
+ PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
+ PR_PRPF &= (uint8_t)~(PR_USART0_bm|PR_TC0_bm); \
+} while(0)
+
+
+#define power_all_disable() \
+do { \
+ PR_PRGEN|= (uint8_t)(PR_RTC_bm|PR_EVSYS_bm); \
+ PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \
+ PR_PRPC |=
(uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
+ PR_PRPD |= (uint8_t)(PR_USART0_bm|PR_SPI_bm|PR_TC0_bm); \
+ PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_TC0_bm); \
+ PR_PRPF |= (uint8_t)(PR_USART0_bm|PR_TC0_bm); \
+} while(0)
+#endif
+
#if defined(__AVR_ATxmega16A4__) \
|| defined(__AVR_ATxmega16D4__) \
|| defined(__AVR_ATxmega32A4__) \
@@ -489,7 +778,6 @@
|| defined(__AVR_ATxmega64A1__) \
|| defined(__AVR_ATxmega64A1U__) \
|| defined(__AVR_ATxmega64A3__) \
-|| defined(__AVR_ATxmega64D3__) \
|| defined(__AVR_ATxmega128A1__) \
|| defined(__AVR_ATxmega128A1U__) \
|| defined(__AVR_ATxmega128A3__) \
@@ -570,13 +858,8 @@
#define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
#define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
-#endif
-
#if defined(__AVR_ATxmega16D4__) \
-|| defined(__AVR_ATxmega32D4__) \
-|| defined(__AVR_ATxmega64D3__) \
-|| defined(__AVR_ATxmega128D3__) \
-|| defined(__AVR_ATxmega192D3__)
+|| defined(__AVR_ATxmega32D4__)
#define power_all_enable() \
do { \
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- [avr-libc-commit] [2406] bug #39783: add CRC definitions and update PR definitions for xmega 64/128/ 192 and 256 d3 devices,
Pitchumani <=