[Bug binutils/19721] New: [libopcodes] [Aarch64] Incorrect aliasing for ORR instruction

[njholcomb at wi dot rr.com]

https://sourceware.org/bugzilla/show_bug.cgi?id=19721

            Bug ID: 19721
           Summary: [libopcodes] [Aarch64] Incorrect aliasing for ORR
                    instruction
           Product: binutils
           Version: 2.26
            Status: NEW
          Severity: normal
          Priority: P2
         Component: binutils
          Assignee: unassigned at sourceware dot org
          Reporter: njholcomb at wi dot rr.com
  Target Milestone: ---

The libopcodes decoder for aarch64 incorrectly aliases ORR instructions with
the zero register but non-zero shift values to MOV instructions without
signifying the shift.

Below is GDB output with register info after executing one such instruction
(0xaa1167e):

(gdb) x/x 0x400588
0x400588 <main+16>:  0xaa1167e
(gdb) x/i $pc
=> 0x400588 <main+16>:  mov   x7, x17
(gdb) info registers
...
x7             0x83322
...
x17            0x4109d8
...
(gdb) stepi
0x000000000040058c in main ()
(gdb) info registers
...
x7             0x8213b0000000
...
x17            0x4109d8
...

The instruction correct interpretation should be the ORR instruction with a
left shift of 25 bits.

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