[Bug binutils/20705] [libopcodes][x86] VEX masking register name lacks formatting, cannot assemble

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=20705

--- Comment #1 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by H.J. Lu <address@hidden>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=9889cbb14ebea4b281408afcfd94ad6646ab370a

commit 9889cbb14ebea4b281408afcfd94ad6646ab370a
Author: H.J. Lu <address@hidden>
Date:   Thu Oct 20 15:07:42 2016 -0700

    Check invalid mask registers

    In 32-bit, the REX_B bit in the 3-byte VEX prefix is ignored and the
    the highest bit in VEX.vvvv is either 1 or ignored.  In 64-bit, we
    need to check invalid mask registers.

    gas/

        PR binutis/20705
        * testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad.
        * testsuite/gas/i386/x86-64-opcode-bad.d: New file.
        * testsuite/gas/i386/x86-64-opcode-bad.s: Likewise.

    opcodes/

        PR binutis/20705
        * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
        the highest bit in VEX.vvvv for the 3-byte VEX prefix in
        32-bit mode.  Don't check vex.register_specifier in 32-bit
        mode.
        (OP_E_register): Check invalid mask registers.
        (OP_G): Likewise.
        (OP_VEX): Likewise.

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