[Bug gas/23192] aarch64: indexed fcmla doesn't support all registers

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=23192

--- Comment #2 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by Tamar Christina
<address@hidden>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=369c9167d47e69aad2e260cc1db17f8c894c138b

commit 369c9167d47e69aad2e260cc1db17f8c894c138b
Author: Tamar Christina <address@hidden>
Date:   Fri Jun 29 12:12:27 2018 +0100

    Fix AArch64 encodings for by element instructions.

    Some instructions in Armv8-a place a limitation on FP16 registers that can
be
    used as the register from which to select an element from.

    e.g. fmla restricts Rm to 4 bits when using an FP16 register.  This
restriction
    does not apply for all instructions, e.g. fcmla does not have this
restriction
    as it gets an extra bit from the M field.

    Unfortunately, this restriction to S_H was added for all _Em operands
before,
    meaning for a large number of instructions you couldn't use the full
register
    file.

    This fixes the issue by introducing a new operand _Em16 which applies this
    restriction only when paired with S_H and leaves the _Em and the other
    qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).

    Also the patch updates all instructions that should be affected by this.

    opcodes/

        PR binutils/23192
        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Likewise.
        * aarch64-opc-2.c: Likewise.
        * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16
constraint.
        * aarch64-opc.c (operand_general_constraint_met_p,
        aarch64_print_operand): Likewise.
        * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
        smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
        fmlal2, fmlsl2.
        (AARCH64_OPERANDS): Add Em2.

    gas/

        PR binutils/23192
        * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
        AARCH64_OPND_Em16
        * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
        16 registers.
        * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
        * testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
        * testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
        * testsuite/gas/aarch64/sve.d: Likewise.

    include/

        PR binutils/23192
        *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.

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