[Bug binutils/19921] enable specification of data width when writing verilog hex format

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=19921

--- Comment #10 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by Nick Clifton <address@hidden>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=37d0d09177dc02e0002ab8b90d9b7bc402af9240

commit 37d0d09177dc02e0002ab8b90d9b7bc402af9240
Author: Jamey Hicks <address@hidden>
Date:   Tue May 14 10:40:04 2019 +0100

    Add new option to objcopy: --verilog-data-width.  Use this option to set
the size of byte bundles generated in verilog format files.

        PR 19921
    binutils* objcopy.c: Add new option --verilog-data-width.  Use it to set
        the value of VerilogDataWidth.
        * doc/binutils.texi: Document the new option.
        * testsuite/binutils-all/objcopy.exp: Run tests of new option.
        * testsuite/binutils-all/verilog-1.hex: New file.
        * testsuite/binutils-all/verilog-2.hex: New file.
        * testsuite/binutils-all/verilog-4.hex: New file.
        * testsuite/binutils-all/verilog-8.hex: New file.
        * NEWS: Mention the new feature.

    bfd * verilog.c: (VerilogDataWidth): New variable.
        (verilog_write_record): Emit bytes in VerilogDataWidth bundles.

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