[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=25202

--- Comment #24 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by Nick Clifton <nickc@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=6ef35c04dffe685ece08212201c4c032baf8aa86

commit 6ef35c04dffe685ece08212201c4c032baf8aa86
Author: Nick Clifton <nickc@redhat.com>
Date:   Thu Dec 1 13:09:26 2022 +0000

    Fix verilog output when the width is > 1.

            PR 25202
    bfd     * bfd.c (VerilogDataEndianness): New variable.
            (verilog_write_record): Use VerilogDataEndianness, if set, to
            choose the endianness of the output.
            (verilog_write_section): Adjust the address by the data width.

    binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
            endianness of the input file.
            (copy_main): Verifiy the value set by the --verilog-data-width
            option.
            * testsuite/binutils-all/objcopy.exp: Add tests of the new
behaviour.
            * testsuite/binutils-all/verilog-I4.hex: New file.

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