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[Bug binutils/30495] New: [libopcodes][riscv] ori x0, xn, imm decoded as
From: |
tommy_murphy at hotmail dot com |
Subject: |
[Bug binutils/30495] New: [libopcodes][riscv] ori x0, xn, imm decoded as incorrect instruction class causing gdb sim to terminate |
Date: |
Sat, 27 May 2023 16:47:36 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=30495
Bug ID: 30495
Summary: [libopcodes][riscv] ori x0, xn, imm decoded as
incorrect instruction class causing gdb sim to
terminate
Product: binutils
Version: 2.40
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: binutils
Assignee: unassigned at sourceware dot org
Reporter: tommy_murphy at hotmail dot com
Target Milestone: ---
Originally discussed here:
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1200
And then I filed it here but I guess that that was the wrong place:
https://sourceware.org/bugzilla/show_bug.cgi?id=30494
As far as I can see (and as outlined here:
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1200#issuecomment-1451965016)
the ori x0, xn, imm instruction is getting decoded as the wrong class
(INSN_CLASS_ZBC_OR_ZBKC instead of INSN_CLASS_I) and the simulator terminates
with an UNHANDLED_EXTENSION message.
If any additional info is needed please let me know - thanks.
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- [Bug binutils/30495] New: [libopcodes][riscv] ori x0, xn, imm decoded as incorrect instruction class causing gdb sim to terminate,
tommy_murphy at hotmail dot com <=