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[Bug gas/32036] RISC-V zcmp: unrecognized opcode `cm.mva01s s0,s1'


From: cvs-commit at gcc dot gnu.org
Subject: [Bug gas/32036] RISC-V zcmp: unrecognized opcode `cm.mva01s s0,s1'
Date: Tue, 27 Aug 2024 02:26:37 +0000

https://sourceware.org/bugzilla/show_bug.cgi?id=32036

--- Comment #3 from Sourceware Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Nelson Chu <nelsonc1225@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ca2590d7804b4ea563eec6f1127ed17a00c30315

commit ca2590d7804b4ea563eec6f1127ed17a00c30315
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Tue Aug 20 10:10:21 2024 +0800

    RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.

    This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'.
    All disassemble instructions use the sreg format.

    Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
    Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
    Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
    Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
    Co-Authored by: Simon Cook <simon.cook@embecosm.com>
    Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
    Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

    gas/ChangeLog:
            PR 32036
            * NEWS: Updated.
            * config/tc-riscv.c (validate_riscv_insn): New operators.
            (riscv_ip): Ditto.
            * testsuite/gas/riscv/zcmp-mv.d: New test.
            * testsuite/gas/riscv/zcmp-mv.s: New test.

    include/ChangeLog:
            PR 32036
            * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode.
            (MASK_CM_MVA01S): New mask.
            (MATCH_CM_MVSA01): New opcode.
            (MASK_CM_MVSA01): New mask.
            (DECLARE_INSN): New declarations.
            * opcode/riscv.h (OP_MASK_SREG1): New mask.
            (OP_SH_SREG1): New operand code.
            (OP_MASK_SREG2): New mask.
            (OP_SH_SREG2): New operand code.
            (X_A0): New reg number.
            (X_A1): Ditto.
            (X_S7): Ditto.
            (RISCV_SREG_0_7): New macro function.

    opcodes/ChangeLog:
            PR 32036
            * riscv-dis.c (riscv_zcmp_get_sregno): New function.
            (print_insn_args): New operators.
            * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.

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