Re: [PATCH v3 gnumach] smp: Rearrange IPI sending mechanism

[Almudena Garcia]

I set the code as this way because it's the standard of Intel's guides. 

The guide explain that although most machines turn on the cpu with an unique 
SIPI, some machines could require a second SIPI. Even some older machines could 
need a INIT IPI before the SIPI.

It's the reason because i wrote the code aa this way, following the advice on 
of Intel's guides. 

El viernes 23 de febrero de 2024, Samuel Thibault escribió:
> Damien Zammit, le ven. 23 févr. 2024 08:14:53 +0000, a ecrit:
> > Wait for ICR then just assert the signal.
> > Linux and NetBSD does it this way, assume they know better.
> 
> But also possibly not. IIRC Almudena had good reasons to set the code
> this way.
> 
> What problem does this actually solve?
> 
> Remember that commit logs should always document the "why the change".
> 
> > ---
> >  i386/i386/smp.c | 8 +-------
> >  1 file changed, 1 insertion(+), 7 deletions(-)
> > 
> > diff --git a/i386/i386/smp.c b/i386/i386/smp.c
> > index 05e9de67..a758eea3 100644
> > --- a/i386/i386/smp.c
> > +++ b/i386/i386/smp.c
> > @@ -54,17 +54,11 @@ static void smp_send_ipi(unsigned apic_id, unsigned 
> > vector)
> >  
> >      cpu_intr_save(&flags);
> >  
> > -    apic_send_ipi(NO_SHORTHAND, FIXED, PHYSICAL, ASSERT, EDGE, vector, 
> > apic_id);
> > -
> >      do {
> >          cpu_pause();
> >      } while(lapic->icr_low.delivery_status == SEND_PENDING);
> >  
> > -    apic_send_ipi(NO_SHORTHAND, FIXED, PHYSICAL, DE_ASSERT, EDGE, vector, 
> > apic_id);
> > -
> > -    do {
> > -        cpu_pause();
> > -    } while(lapic->icr_low.delivery_status == SEND_PENDING);
> > +    apic_send_ipi(NO_SHORTHAND, FIXED, PHYSICAL, ASSERT, EDGE, vector, 
> > apic_id);
> >  
> >      cpu_intr_restore(flags);
> >  }
> > -- 
> > 2.43.0
> > 
> > 
> > 
> 
> -- 
> Samuel
> ---
> Pour une évaluation indépendante, transparente et rigoureuse !
> Je soutiens la Commission d'Évaluation de l'Inria.
> 
>

-- 
Enviado desde mi dispositivo Sailfish