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[Commit-gnuradio] r6554 - gnuradio/branches/developers/matt/u2f/firmware
|
From: |
eb |
|
Subject: |
[Commit-gnuradio] r6554 - gnuradio/branches/developers/matt/u2f/firmware |
|
Date: |
Thu, 27 Sep 2007 12:18:13 -0600 (MDT) |
Author: eb
Date: 2007-09-27 12:18:12 -0600 (Thu, 27 Sep 2007)
New Revision: 6554
Modified:
gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
gnuradio/branches/developers/matt/u2f/firmware/eth_test.c
gnuradio/branches/developers/matt/u2f/firmware/memory_map.h
gnuradio/branches/developers/matt/u2f/firmware/test1_main.c
gnuradio/branches/developers/matt/u2f/firmware/u2_init.c
Log:
refactored some firmware; currently passes tests under simulation
Modified: gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
2007-09-27 15:10:50 UTC (rev 6553)
+++ gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
2007-09-27 18:18:12 UTC (rev 6554)
@@ -2,3 +2,11 @@
#include "buffer_pool.h"
#include "sim_io.h"
+void
+bp_init(void)
+{
+ bp_disable_port(PORT_SERDES);
+ bp_disable_port(PORT_DSP);
+ bp_disable_port(PORT_ETH);
+ bp_disable_port(PORT_RAM);
+}
Modified: gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
2007-09-27 15:10:50 UTC (rev 6553)
+++ gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
2007-09-27 18:18:12 UTC (rev 6554)
@@ -5,28 +5,70 @@
// Buffer Pool Management
+void bp_init(void);
+
+#if 1
+
static inline void
-clear_buf(int bufnum) {
- volatile int *addr = (int *)BUFFER_POOL_BASE;
+bp_clear_buf(int bufnum)
+{
+ buffer_pool_ctrl->ctrl = BPC_BUFFER(bufnum) | BPC_PORT_NIL | BPC_CLR;
+}
+
+static inline void
+bp_disable_port(int portnum)
+{
+ // disable buffer connections to this port
+ buffer_pool_ctrl->ctrl = BPC_BUFFER_NIL | BPC_PORT(portnum);
+}
+
+static inline void
+bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll)
+{
+ buffer_pool_ctrl->ctrl = (BPC_READ
+ | BPC_BUFFER(bufnum)
+ | BPC_PORT(port)
+ | BPC_STEP(step)
+ | BPC_FIRST_LINE(fl)
+ | BPC_LAST_LINE(ll));
+}
+
+static inline void
+bp_send_from_buf(int bufnum, int port, int step, int fl, int ll)
+{
+ buffer_pool_ctrl->ctrl = (BPC_WRITE
+ | BPC_BUFFER(bufnum)
+ | BPC_PORT(port)
+ | BPC_STEP(step)
+ | BPC_FIRST_LINE(fl)
+ | BPC_LAST_LINE(ll));
+}
+
+#else
+
+static inline void
+bp_clear_buf(int bufnum) {
+ volatile int *addr = (int *)BUFFER_POOL_RAM_BASE;
*addr = (bufnum << 28) | (4<<25) | (1<<24); // disable port connections to
this buffer, clear state
}
static inline void
-disable_port(int portnum) {
- volatile int *addr = (int *)(BUFFER_POOL_BASE);
+bp_disable_port(int portnum) {
+ volatile int *addr = (int *)(BUFFER_POOL_RAM_BASE);
*addr = (8 << 28) | (portnum<<25); // disable buffer connections to this port
}
static inline void
-receive_to_buf(int bufnum, int port, int step, int fl, int ll) {
- volatile int *addr = (int *)(BUFFER_POOL_BASE);
+bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll) {
+ volatile int *addr = (int *)(BUFFER_POOL_RAM_BASE);
*addr = (bufnum<<28) | (port << 25) | (1<<23) | (step<<18) | (ll<<9) | fl;
}
static inline void
-send_from_buf(int bufnum, int port, int step, int fl, int ll) {
- volatile int *addr = (int *)(BUFFER_POOL_BASE);
+bp_send_from_buf(int bufnum, int port, int step, int fl, int ll) {
+ volatile int *addr = (int *)(BUFFER_POOL_RAM_BASE);
*addr = (bufnum<<28) | (port << 25) | (1<<22) | (step<<18) | (ll<<9) | fl;
}
+#endif
#endif
Modified: gnuradio/branches/developers/matt/u2f/firmware/eth_test.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/eth_test.c 2007-09-27
15:10:50 UTC (rev 6553)
+++ gnuradio/branches/developers/matt/u2f/firmware/eth_test.c 2007-09-27
18:18:12 UTC (rev 6554)
@@ -29,9 +29,14 @@
sim_puts("Start Program\n");
// Write data to be sent into the first buffer
- int *buffer0 = (int *)(BUFFER_BASE + BUFFER_0);
- int *buffer1 = (int *)(BUFFER_BASE + BUFFER_1);
+ //int *buffer0 = (int *)(BUFFER_BASE + BUFFER_0);
+ //int *buffer1 = (int *)(BUFFER_BASE + BUFFER_1);
+ volatile unsigned int *buffer0 = buffer_ram(0);
+ volatile unsigned int *buffer1 = buffer_ram(1);
+ sim_puts("Buffer0 ="); sim_puthex_nl((int) buffer0);
+ sim_puts("Buffer1 ="); sim_puthex_nl((int) buffer1);
+
// Buffer status info
volatile unsigned int *status = (unsigned int *) 0xB020;
@@ -41,49 +46,49 @@
sim_puts("Filled in RAM\n");
// Set up receive buffer
- receive_to_buf(1, 2, 1, 0, 511); // Fill from ethernet
+ bp_receive_to_buf(1, 2, 1, 0, 511); // Fill from ethernet
sim_puts("Set up RX buffer\n");
// Set up send buffer
- send_from_buf(0, 2, 1, 0, 20);
+ bp_send_from_buf(0, 2, 1, 0, 20);
sim_puts("Set up TX Buffer\n");
while(*status != 3) {}
- clear_buf(0);
- clear_buf(1);
+ bp_clear_buf(0);
+ bp_clear_buf(1);
sim_puts("Both are done\n");
// Send a bunch, let them pile up in FIFO
- send_from_buf(0, 2, 1, 21, 80); while(*status == 0) {}
- clear_buf(0);
+ bp_send_from_buf(0, 2, 1, 21, 80); while(*status == 0) {}
+ bp_clear_buf(0);
sim_puts("First add'l TX done\n");
- send_from_buf(0, 2, 1, 81, 288); while(*status == 0) {}
- clear_buf(0);
- send_from_buf(0, 2, 1, 289, 292); while(*status == 0) {}
- clear_buf(0);
- send_from_buf(0, 2, 1, 293, 326); while(*status == 0) {}
- clear_buf(0);
- send_from_buf(0, 2, 1, 327, 399); while(*status == 0) {}
- clear_buf(0);
- send_from_buf(0, 2, 1, 400, 511); while(*status == 0) {}
- clear_buf(0);
+ bp_send_from_buf(0, 2, 1, 81, 288); while(*status == 0) {}
+ bp_clear_buf(0);
+ bp_send_from_buf(0, 2, 1, 289, 292); while(*status == 0) {}
+ bp_clear_buf(0);
+ bp_send_from_buf(0, 2, 1, 293, 326); while(*status == 0) {}
+ bp_clear_buf(0);
+ bp_send_from_buf(0, 2, 1, 327, 399); while(*status == 0) {}
+ bp_clear_buf(0);
+ bp_send_from_buf(0, 2, 1, 400, 511); while(*status == 0) {}
+ bp_clear_buf(0);
sim_puts("All add'l TX done\n");
- receive_to_buf(1, 2, 1, 21, 80); while(*status == 0) {}
- clear_buf(1);
+ bp_receive_to_buf(1, 2, 1, 21, 80); while(*status == 0) {}
+ bp_clear_buf(1);
sim_puts("First add'l RX done\n");
- receive_to_buf(1, 2, 1, 81, 288); while(*status == 0) {}
- clear_buf(1);
- receive_to_buf(1, 2, 1, 289, 292); while(*status == 0) {}
- clear_buf(1);
- receive_to_buf(1, 2, 1, 293, 326); while(*status == 0) {}
- clear_buf(1);
- receive_to_buf(1, 2, 1, 327, 399); while(*status == 0) {}
- clear_buf(1);
- receive_to_buf(1, 2, 1, 400, 511); while(*status == 0) {}
- clear_buf(1);
+ bp_receive_to_buf(1, 2, 1, 81, 288); while(*status == 0) {}
+ bp_clear_buf(1);
+ bp_receive_to_buf(1, 2, 1, 289, 292); while(*status == 0) {}
+ bp_clear_buf(1);
+ bp_receive_to_buf(1, 2, 1, 293, 326); while(*status == 0) {}
+ bp_clear_buf(1);
+ bp_receive_to_buf(1, 2, 1, 327, 399); while(*status == 0) {}
+ bp_clear_buf(1);
+ bp_receive_to_buf(1, 2, 1, 400, 511); while(*status == 0) {}
+ bp_clear_buf(1);
sim_puts("All add'l RX done\n");
for(i=0;i<512;i++)
Modified: gnuradio/branches/developers/matt/u2f/firmware/memory_map.h
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/memory_map.h 2007-09-27
15:10:50 UTC (rev 6553)
+++ gnuradio/branches/developers/matt/u2f/firmware/memory_map.h 2007-09-27
18:18:12 UTC (rev 6554)
@@ -1,29 +1,36 @@
#ifndef INCLUDED_MEMORY_MAP_H
#define INCLUDED_MEMORY_MAP_H
-/**********************************************************
- * Memory map for embedded wishbone bus
- **********************************************************
- */
+////////////////////////////////////////////////////////////////
+//
+// Memory map for embedded wishbone bus
+//
+////////////////////////////////////////////////////////////////
-/////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////
// Main RAM, Slave 0
+
#define RAM_BASE 0x0000
-/////////////////////////////////////////////////////
-// Buffer RAM, Slave 1
-#define BUFFER_BASE 0x4000
-#define BUFFER_SIZE 0x0200 // Buffer size in 32-bit lines
-#define BUFFER_0 0x0000
-#define BUFFER_1 0x0800
-#define BUFFER_2 0x1000
-#define BUFFER_3 0x1800
-#define BUFFER_4 0x2000
-#define BUFFER_5 0x2800
-#define BUFFER_6 0x3000
-#define BUFFER_7 0x3800
+////////////////////////////////////////////////////////////////
+// Buffer Pool RAM, Slave 1
+//
+// The buffers themselves are located in Slave 1, Buffer Pool RAM.
+// The status registers are in Slave 5, Buffer Pool Status.
+// The control register is in Slave 7, Settings Bus.
+#define BUFFER_POOL_RAM_BASE 0x4000
+#define NBUFFERS 8
+#define BUFFER_POOL_BUFFER_SIZE 0x0200 // Buffer size in 32-bit lines
+
+#define buffer_pool_ram \
+ ((volatile unsigned int *) BUFFER_POOL_RAM_BASE)
+
+#define buffer_ram(n) (&buffer_pool_ram[(n) * BUFFER_POOL_BUFFER_SIZE])
+
+
/////////////////////////////////////////////////////
// SPI Core, Slave 2. See core docs for more info
#define SPI_BASE 0x8000 // Base address (16-bit)
@@ -33,27 +40,27 @@
#define SPI_TXRX1 0x004
#define SPI_TXRX2 0x008
#define SPI_TXRX3 0x00c
-#define SPI_CTRL 0x010
-#define SPI_DIV 0x014
-#define SPI_SS 0x018
+#define SPI_CTRL 0x010
+#define SPI_DIV 0x014
+#define SPI_SS 0x018
// Masks for controlling different peripherals
-#define SPI_SS_AD9510 1
-#define SPI_SS_AD9777 2
-#define SPI_SS_RX_DAC 4
-#define SPI_SS_RX_ADC 8
-#define SPI_SS_RX_DB 16
-#define SPI_SS_TX_DAC 32
-#define SPI_SS_TX_ADC 64
+#define SPI_SS_AD9510 1
+#define SPI_SS_AD9777 2
+#define SPI_SS_RX_DAC 4
+#define SPI_SS_RX_ADC 8
+#define SPI_SS_RX_DB 16
+#define SPI_SS_TX_DAC 32
+#define SPI_SS_TX_ADC 64
#define SPI_SS_TX_DB 128
// Masks for different parts of CTRL reg
-#define SPI_CTRL_ASS 1<<13
-#define SPI_CTRL_IE 1<<12
-#define SPI_CTRL_LSB 1<<11
-#define SPI_CTRL_TXNEG 1<<10
-#define SPI_CTRL_RXNEG 1<<9
-#define SPI_CTRL_GO_BSY 1<<8
+#define SPI_CTRL_ASS (1<<13)
+#define SPI_CTRL_IE (1<<12)
+#define SPI_CTRL_LSB (1<<11)
+#define SPI_CTRL_TXNEG (1<<10)
+#define SPI_CTRL_RXNEG (1<< 9)
+#define SPI_CTRL_GO_BSY (1<< 8)
#define SPI_CTRL_CHAR_LEN 0x7F
#define SPI_TXONLY 0
@@ -102,7 +109,7 @@
////////////////////////////////////////////////
// GPIO, Slave 4
-
+//
// These go to the daughterboard i/o pins
#define GPIO_BASE 0xA000
@@ -117,8 +124,39 @@
#define gpio_base ((gpio_regs_t *) GPIO_BASE)
///////////////////////////////////////////////////
-// Buffer Pool status, Slave 5
+// Buffer Pool Status, Slave 5
+//
+// The buffers themselves are located in Slave 1, Buffer Pool RAM.
+// The status registers are in Slave 5, Buffer Pool Status.
+// The control register is in Slave 7, Settings Bus.
+#define BUFFER_POOL_STATUS_BASE 0xB000
+
+typedef struct {
+ volatile unsigned last_line[8]; // last line xfer'd in buffer
+ volatile unsigned status; // error and done flags
+} buffer_pool_status_t;
+
+#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE)
+
+#define BPS_DONE_0 0x0001 // buffer 0 xfer is done
+#define BPS_DONE_1 0x0002 // buffer 1 xfer is done
+#define BPS_DONE_2 0x0004 // buffer 2 xfer is done
+#define BPS_DONE_3 0x0008 // buffer 3 xfer is done
+#define BPS_DONE_4 0x0010 // buffer 4 xfer is done
+#define BPS_DONE_5 0x0020 // buffer 5 xfer is done
+#define BPS_DONE_6 0x0040 // buffer 6 xfer is done
+#define BPS_DONE_7 0x0080 // buffer 7 xfer is done
+#define BPS_ERROR_0 0x0100 // buffer 0 xfer had error
+#define BPS_ERROR_1 0x0200 // buffer 1 xfer had error
+#define BPS_ERROR_2 0x0400 // buffer 2 xfer had error
+#define BPS_ERROR_3 0x0800 // buffer 3 xfer had error
+#define BPS_ERROR_4 0x1000 // buffer 4 xfer had error
+#define BPS_ERROR_5 0x2000 // buffer 5 xfer had error
+#define BPS_ERROR_6 0x4000 // buffer 6 xfer had error
+#define BPS_ERROR_7 0x8000 // buffer 7 xfer had error
+
+
///////////////////////////////////////////////////
// Ethernet Core, Slave 6
@@ -135,22 +173,63 @@
// 1KB of address space (== 256 32-bit write-only regs)
-// Simple outputs
-#define OUTPUTS_BASE 0xD000
+#define MISC_OUTPUT_BASE 0xD000
+#define BUFFER_POOL_CTRL_BASE 0xD100
+#define DSP_TX_BASE 0xD200
+#define DSP_RX_BASE 0xD280
-#define BUFFER_POOL_BASE 0xD100
-#define DSP_TX_BASE 0xD200
-#define DSP_RX_BASE 0xD280
+#define LAST_SETTING_REG 0xD3FC // last valid setting register
-#define LAST_SETTING 0xD3FC // last valid setting register
+// --- buffer pool control regs ---
+typedef struct {
+ volatile unsigned int ctrl;
+} buffer_pool_ctrl_t;
-#define SERDES_ENABLE 8
-#define SERDES_PRBSEN 4
-#define SERDES_LOOPEN 2
-#define SERDES_RXEN 1
+// buffer pool ports
+#define PORT_SERDES 0 // serial/deserializer
+#define PORT_DSP 1 // DSP tx or rx pipeline
+#define PORT_ETH 2 // ethernet tx or rx
+#define PORT_RAM 3 // RAM tx or rx
+// the buffer pool ctrl register fields
+
+#define BPC_BUFFER(n) (((n) & 0xf) << 28)
+#define BPC_BUFFER_MASK PBC_BUFFER(~0)
+#define BPC_BUFFER_0 BPC_BUFFER(0)
+#define BPC_BUFFER_1 BPC_BUFFER(1)
+#define BPC_BUFFER_2 BPC_BUFFER(2)
+#define BPC_BUFFER_3 BPC_BUFFER(3)
+#define BPC_BUFFER_4 BPC_BUFFER(4)
+#define BPC_BUFFER_5 BPC_BUFFER(5)
+#define BPC_BUFFER_6 BPC_BUFFER(6)
+#define BPC_BUFFER_7 BPC_BUFFER(7)
+#define BPC_BUFFER_NIL BPC_BUFFER(0x8) // disable
+
+#define BPC_PORT(n) (((n) & 0x7) << 25)
+#define BPC_PORT_MASK PBC_PORT(~0)
+#define BPC_PORT_SERDES BPC_PORT(PORT_SERDES)
+#define BPC_PORT_DSP BPC_PORT(PORT_DSP)
+#define BPC_PORT_ETH BPC_PORT(PORT_ETH)
+#define BPC_PORT_RAM BPC_PORT(PORT_RAM)
+#define BPC_PORT_NIL BPC_PORT(0x4) // disable
+
+#define BPC_CLR (1 << 24) // mutually excl commands
+#define BPC_READ (1 << 23)
+#define BPC_WRITE (1 << 22)
+
+#define BPC_STEP(step) (((step) & 0xf) << 18)
+#define BPC_STEP_MASK BPC_STEP(~0)
+#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9)
+#define BPC_LAST_LINE_MASK BPC_LAST_LINE(~0)
+#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0)
+#define PBC_FIRST_LINE_MASK BPC_FIRST_LINE(~0)
+
+#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
+
+// --- misc outputs ---
+
typedef struct {
volatile unsigned long clk_ctrl;
volatile unsigned long serdes_ctrl;
@@ -158,8 +237,15 @@
volatile unsigned long leds;
} output_regs_t;
-#define output_regs ((output_regs_t *) OUTPUTS_BASE)
+#define SERDES_ENABLE 8
+#define SERDES_PRBSEN 4
+#define SERDES_LOOPEN 2
+#define SERDES_RXEN 1
+#define output_regs ((output_regs_t *) MISC_OUTPUT_BASE)
+
+// --- dsp tx regs ---
+
typedef struct {
volatile int freq;
volatile short scale_i;
@@ -170,6 +256,8 @@
#define dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE)
+// --- dsp rx regs ---
+
typedef struct {
volatile int freq;
volatile short scale_i;
@@ -207,7 +295,7 @@
typedef struct {
- volatile int edge_enable;
+ volatile int edge_enable; // mask: 1 -> edge triggered, 0 -> level
volatile int polarity; // mask: 1 -> rising edge
volatile int mask; // mask: 1 -> disabled
volatile int pending; // mask: 1 -> pending; write 1's to
clear pending ints
@@ -226,4 +314,5 @@
#define timer_regs ((timer_regs_t *) TIMER_BASE)
+
#endif
Modified: gnuradio/branches/developers/matt/u2f/firmware/test1_main.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/test1_main.c 2007-09-27
15:10:50 UTC (rev 6553)
+++ gnuradio/branches/developers/matt/u2f/firmware/test1_main.c 2007-09-27
18:18:12 UTC (rev 6554)
@@ -64,7 +64,7 @@
// Set up DSP RX
buffer_state[0] = FILLING;
serdes_tx_idle = 1;
- receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 0, use 500 lines
+ bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 0, use 500 lines
dsp_rx_regs->run_rx = 1; // Start DSP_RX
sim_puts("Done DSP RX setup\n");
@@ -72,7 +72,7 @@
// Set up serdes RX
buffer_state[2] = FILLING;
dsp_tx_idle = 1;
- receive_to_buf(2, PORT, 1, 5, 504);
+ bp_receive_to_buf(2, PORT, 1, 5, 504);
volatile unsigned int *status = (unsigned int *) 0xB020;
@@ -101,18 +101,18 @@
unsigned int localstatus = *status;
if(localstatus & 1) {
- clear_buf(0);
+ bp_clear_buf(0);
if(buffer_state[0] == FILLING) {
buffer_state[0] = FULL;
if(buffer_state[1] == EMPTY) {
- receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines
+ bp_receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500
lines
buffer_state[1] = FILLING;
}
else
dsp_rx_idle = 1;
if(serdes_tx_idle) {
serdes_tx_idle = 0;
- send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0
+ bp_send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0
buffer_state[0] = EMPTYING;
}
}
@@ -120,11 +120,11 @@
buffer_state[0] = EMPTY;
if(dsp_rx_idle) {
dsp_rx_idle = 0;
- receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 0, use 500 lines
+ bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 0, use 500
lines
buffer_state[0] = FILLING;
}
if(buffer_state[1] == FULL) {
- send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1
+ bp_send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1
buffer_state[1] = EMPTYING;
}
else
@@ -133,18 +133,18 @@
sim_puts("Int Proc'ed 0\n");
}
if(localstatus & 2) {
- clear_buf(1);
+ bp_clear_buf(1);
if(buffer_state[1] == FILLING) {
buffer_state[1] = FULL;
if(buffer_state[0] == EMPTY) {
- receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines
+ bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500
lines
buffer_state[0] = FILLING;
}
else
dsp_rx_idle = 1;
if(serdes_tx_idle) {
serdes_tx_idle = 0;
- send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1
+ bp_send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1
buffer_state[1] = EMPTYING;
}
}
@@ -152,11 +152,11 @@
buffer_state[1] = EMPTY;
if(dsp_rx_idle) {
dsp_rx_idle = 0;
- receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines
+ bp_receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500
lines
buffer_state[1] = FILLING;
}
if(buffer_state[0] == FULL) {
- send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0
+ bp_send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0
buffer_state[0] = EMPTYING;
}
else
@@ -165,18 +165,18 @@
sim_puts("Int Proc'ed 1\n");
}
if(localstatus & 4) {
- clear_buf(2);
+ bp_clear_buf(2);
if(buffer_state[2] == FILLING) {
buffer_state[2] = FULL;
if(buffer_state[3] == EMPTY) {
- receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3, use 500
lines
+ bp_receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3, use
500 lines
buffer_state[3] = FILLING;
}
else
serdes_rx_idle = 1;
if(dsp_tx_idle) {
dsp_tx_idle = 0;
- send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2
+ bp_send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2
buffer_state[2] = EMPTYING;
}
}
@@ -184,11 +184,11 @@
buffer_state[2] = EMPTY;
if(serdes_rx_idle) {
serdes_rx_idle = 0;
- receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2
+ bp_receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2
buffer_state[2] = FILLING;
}
if(buffer_state[3] == FULL) {
- send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3
+ bp_send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3
buffer_state[3] = EMPTYING;
}
else
@@ -197,18 +197,18 @@
sim_puts("Int Proc'ed 2\n");
}
if(localstatus & 8) {
- clear_buf(3);
+ bp_clear_buf(3);
if(buffer_state[3] == FILLING) {
buffer_state[3] = FULL;
if(buffer_state[2] == EMPTY) {
- receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2, use 500
lines
+ bp_receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2, use
500 lines
buffer_state[2] = FILLING;
}
else
serdes_rx_idle = 1;
if(dsp_tx_idle) {
dsp_tx_idle = 0;
- send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3
+ bp_send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3
buffer_state[3] = EMPTYING;
}
}
@@ -216,11 +216,11 @@
buffer_state[3] = EMPTY;
if(serdes_rx_idle) {
serdes_rx_idle = 0;
- receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3
+ bp_receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3
buffer_state[3] = FILLING;
}
if(buffer_state[2] == FULL) {
- send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2
+ bp_send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2
buffer_state[2] = EMPTYING;
}
else
@@ -264,18 +264,18 @@
#if 0
// rx SERDES into buffer #2 (buf,port,step,fl,ll)
- receive_to_buf(2, 0, 1, 10, 300);
+ bp_receive_to_buf(2, 0, 1, 10, 300);
sim_puts("SERDES RX buffer setup\n");
// send SERDES from buffer #0 (buf,port,step,fl,ll)
- send_from_buf(0, 0, 1, 20, 200);
+ bp_send_from_buf(0, 0, 1, 20, 200);
sim_puts("SERDES TX buffer setup\n");
#endif
#if 0
// send to DACs from buffer #1
- send_from_buf(1 /*buf#*/, 1 /*port*/, 1 /*step*/, 20 /*fl*/, 250 /*ll*/);
+ bp_send_from_buf(1 /*buf#*/, 1 /*port*/, 1 /*step*/, 20 /*fl*/, 250 /*ll*/);
sim_puts("DAC Buffer setup\n");
#endif
@@ -285,7 +285,7 @@
if(*status & (1<<i)) {
//sim_puts("Clearing buf ");
sim_puthex_nl(i);
- clear_buf(i);
+ bp_clear_buf(i);
}
//sim_puts("EXIT INT\n");
#endif
Modified: gnuradio/branches/developers/matt/u2f/firmware/u2_init.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/u2_init.c 2007-09-27
15:10:50 UTC (rev 6553)
+++ gnuradio/branches/developers/matt/u2f/firmware/u2_init.c 2007-09-27
18:18:12 UTC (rev 6554)
@@ -4,6 +4,7 @@
#include "spi.h"
#include "pic.h"
#include "sim_io.h"
+#include "buffer_pool.h"
/*
* We ought to arrange for this to be called before main, but for now,
@@ -65,5 +66,6 @@
// sim_puts("Setting up interrupt controller\n");
pic_init();
+ bp_init();
return 1;
}
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