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Re: Preprocessing files with make


From: Erik Cato
Subject: Re: Preprocessing files with make
Date: 19 Aug 2004 06:53:05 -0700

"Colin S. Miller" <colin.miller@spam-me-not.picsel.com> wrote in message 
news:<idu1gc.5s7.ln@195.171.216.1>...
> Make isn't concerned about what format
> the source files are in, you
> neeed to know how to make gcc (or compiler
> of your choice) preprocess a C file,
> but not compile it. For gcc it's the
> '-E' option.
> 

> HTH,
> Colin S. Miller

It seems that i still havent made myslef clear.

The preprocessing of the files isnt the problem. 
Because I want to search for source files I dont know what files it will
find and therefor I can not construct any rule for it. 

Let me show what I have so far 

#------------------------------------------------------
# Makefile sample
#------------------------------------------------------
PREPROCDIR   = $(TARGETDIR)/Preproc

COMMON_SRC_DIRS = Source/Dir1 \
                  Source/Dir2 \
                  Source/Dir3 

#------------------------------------------------------
#             Tools options
#------------------------------------------------------
CPP         = "C:\Program Files\IAR Systems\Ew23\avr\bin\iccavr"

CPP_CMD_LINE   = $< --preprocess=n $@

#------------------------------------------------------
#             Files and directorys
#------------------------------------------------------
VPATH    = $(COMMON_SRC_DIRS) 
SRCS     = $(foreach dir,$(VPATH),$(wildcard $(dir)/*.c))
PREPROCS = $(notdir $(patsubst %.c,%.d,$(SRCS)))

#------------------------------------------------------

This will create one varianble with the sourcefiles names ((SRCS)
and one with the preprocessed filenames (PREPROCS).

But what i wand to know now is how do i construct the rule that makes
the preprocessor to be called one time for every source-file.
The commandline for the preprocessor itself is not important. That
part i think i can handle.

I hope I made my intentions clear this time!

/Erik


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