parameter replacement in make during rule execution

[vincent . stay]

Hi,
I have a makefile which generates a tcl file when a certain target is made:

DO_SIM:
        [many echo commands] >> sim.tcl
        for option in $(OPTIONS); do            \
                echo -n "$(if $(findstring =,$$option),$$option,$$option=) " >> 
sim.tcl;        \
        done;
        [more echo command] >> sim.tcl

my problem is with the for loop shown. OPTIONS variable has various fields in 
it. Some fields have a '=' in them ie. FOO=512 and some don't. Because I have a 
broken tool which gets confused by variables which don't have an equal sign in 
them I am trying to go through them and convert "FOO=512 BAR" into "FOO=512 
BAR=". The trouble is that the findstring never finds anything and I get 
"FOO=512= BAR=". When I replace the whole findstring command with 1, I get the 
then case of the 'if' but no amount trial made findstring work. Any ideas what 
my problem is or how to do what I need differently?

Thanks.

By the way, I am running make under cygwin and my make version is 4.0.2 if that 
makes a difference.