Re: Macros and include?

[Paul D. Smith]

%% address@hidden writes:

  tl> I have a small problem that I'm trying to solve. I'd like somehow
  tl> to reduce the following include statements in make to some sort of
  tl> loop, e.g

  tl> MODDIR := submod1
  tl> include $(MODDIR)/module.mk

  tl> MODDIR := submod2
  tl> include $(MODDIR)/module.mk

  tl> ...

  tl> Change to:

  tl> MODDIRS := submod1 submod2
  tl> Some sort of iteration of MODDIRS 
  tl> {
  tl> MODDIR := ${dir}
  tl> include ${dir}/module.mk
  tl> }

  tl> Does anyone know how to do this, or if its possible? 

It's not possible using "traditional" make constructs.

If you get GNU make 3.80 you can use the $(eval ...) function to do it,
something like:

  MODDIR_LIST = submod1 submod2 ...

  define INCLUDE_MODDIR
    MODDIR := $$1
    include $$1/module.mk
  endef

  $(foreach D,$(MODDIR_LIST),$(eval $(call INCLUDE_MODDIR,$D)))

or something like that; I didn't actually try the above so it might not
be quite right in the quoting, etc.

Also note that there are a few bugs in eval in 3.80; these have been
fixed in the source and will be available in the next version of GNU
make.

-- 
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