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undocumented make features
From: |
Boris Kolpackov |
Subject: |
undocumented make features |
Date: |
Thu, 3 Jul 2003 18:31:54 +0000 (UTC) |
User-agent: |
nn/6.6.5+RFC1522 |
Good day,
I have a few questions about undocumented/surprising behavior of
gnu make.
Consider the following Makefile:
-------------
# Makefile
define set
$(eval $1:=$2)
endef
$(call set,foo,bar)
all:; @echo $(foo)
-------------
It works fine with make 3.80 even though manual doesn't say it's legal
to use $(call ) like this.
Also the following pair of Makefile's works fine:
-------------
# Included.mk
foo := bar
-------------
-------------
# Makefile
define include
$(eval include $1)
endef
$(call include,Included.mk)
all:; @echo $(foo)
-------------
Even though 'include' is a keyword.
So the question is whether it's ok to rely on such features or not.
thanks,
-boris
PS. BTW, is there some schedule for make 3.81 release?
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