Make does expand implicit rules, patterns, $(eval $(call)) constructs, etc.
In the end the whole thing become somewhat undeterministic as far as human
perception goes.
And make -p (print the rule database) does not help, as its a tangled mess
of funky s**t---many little twisty passages, all different.
So, i propose to create a Makefile compiler, which will create simpler makefiles
with following properties from the base complex version:
- no implicit rules
- no patterns
- no eval/call constructs
- everything else is left intact
- all of the expansions in the resulting makefile have to be made
in-place
I do realise that the resulting makefile will be strictly bound to the existing
file set present in the file tree at the time of compilation -- and that is
perfectly ok, for we still have the makefile source and can recompile.
What do you think?
All feedback, either positive or negative is extremely welcome.