Re: variable expansion in pattern rule prerequisites

[Nathan Straz]

Boris writes:
> Nathan Straz <address@hidden> writes:
> > I have a makefile like this:
> > ------------------------------
> > $(LIBBAR): ../lib/libbar.a
> >       $(MAKE) -C ../lib libbar.a
> > $(LIBFAR): ../lib/libfar.a
> >       $(MAKE) -C ../lib libfar.a
> > 
> > LIBS_foo := $(LIBBAR)
> > LIBS_boo := $(LIBFAR)
> > 
> > %: %.c $(LIBS_%)
> >       $(CC) -o $@ $< $(CFLAGS) $(LDFLAGS) $(LIBS_$@)
> > ------------------------------
> 
> You cannot do (at least not in mainline GNU make):
> 
> %: %.c $(LIBS_%)
> 
> The $(LIBS_%) expansion happens when makefile is read and stem (%) 
> substitution happens later when the rule is tried.

Ah, that explains why.  Thank you.

> > Can this be done with pattern rules?
> 
> Why don't you just tell make directly what you want:
> 
> foo: $(LIBBAR)
> boo: $(LIBFAR)
> 
> %: %.c
>         $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^

I guess I had it stuck in my mind that you could only have one rule per
target.  I didn't realize that $^ would pull in all prereqs, not just
the ones in that rule.

Many thanks,
--
Nate Straz                                              address@hidden
sgi, inc                                           http://www.sgi.com/
Linux Test Project                                  http://ltp.sf.net/