Variable substutution for conditionals

[bwhughe]

I have an development environment that currently
supports OS/2 and Windows and I want to add Linux.
A portion of a typical makefile looks like the
following:

!IF "$(PLATFORM)" == "OS2"
!IF "$(DEBUG)" == "YES"
#---------------------------------------------- 
#
#Flags for debugging under OS/2
CFLAGS = /Ti+ /O- /C+ /Wall /G5 /D$(PLATFORM)
LFLAGS = /DEBUG /MAP /out:$(EXE)pager.exe
#----------------------------------------------------------------------------
#
!ELSE
#----------------------------------------------------------------------------
#
#Flags for no debugging under OS/2
CFLAGS = /Ti- /O+ /C+ /Wall /G5 /D$(PLATFORM) 
LFLAGS = /out:$(EXE)pager.exe
#----------------------------------------------------------------------------

!ENDIF
!ENDIF

The !ENDIF !ELSE !ENDIF conditionals work on OS/2
and Windows with both the IBM and Microsoft make
utilities.
The GCC make requires ifeq else and endif. If I
change the !IF !ELSE !ENDIF conditionals to ifeq
else endif the make file will work (after adding
code for the Linux flag settings). However, I want
to have just one make file regardless of the
compiler or OS being used.

I tried setting environment variables for ifeq
else endif and then using the variables in the
make file, i.e. (from the bash shell).

IFEQ=ifeq
ELSE=else
ENDIF=endif
PLATFORM=LINUX
DEBUG=YES

$(IF) "$(PLATFORM)" "OS2"

$(IF) "$(DEBUG)" "YES"
#----------------------------------------------------------------------------
#
#Flags for debugging under OS/2
CFLAGS = /Ti+ /O- /C+ /W3 /Wall+ppt-uni-ext- /Q
/Sp1 /G5 /DBITS /D$(PLATFORM) /D
LFLAGS = /DEBUG /MAP /out:$(EXE)pager.exe
#----------------------------------------------------------------------------
#
$(ELSE)
#----------------------------------------------------------------------------
#
#Flags for no debugging under OS/2
CFLAGS = /Ti- /O+ /C+ /W3 /Wall+ppt-uni-ext- /Q
/Sp1 /G5 /DBITS /D$(PLATFORM) /D
LFLAGS = /out:$(EXE)pager.exe
#----------------------------------------------------------------------------
#
$(ENDIF)
$(ENDIF)

When I run make -f makefile I get the following error:

*** missing separator. Stop.

Can I assume that the conditionals cannot be
substituted with variables?

If I run the makefile with hardcoded ifeq else
endif it works fine so there must be a problem
with using variables for the conditionals.

Any help would be appreciated. My goal is simply
to have one makefile. If I cannot substitute
variables for conditional statements then this
will not be possible.