Make template, ifeq, foreach and eval problem

[Eric West]

I am encountering a problem with a block of script that has me
completely mystified. In a nutshell I am attempting to create a
template that will generate two different build targets. Which target
gets generated depends on the number of targets assigned to a variable
in the main Makefile.

The code in the template is summarized as

include target_defs.mk

ifeq ("$(words ${module})", "1")
    # Default, only one module to build from sources in a target directory.
   ${module} : platform_module
else
    # Assumes each module has a corresponding <module>_source
    #
    $(foreach m,${module}, \
        $(eval $(call make-module-tgt, ${m}, $(subst .c,.o, ${${m}_sources})) ) \
    )
endif

The function/macro defined in the included file is:

# $(call make-module-tgt, target, obj_list )
define make-module-tgt
${1}: ${2}
    ${LD} ${LDFLAGS} -o ${1} ${2} ${LIBS}
endef


With this code, make fails with "*** missing `endif'.  Stop."

If I replace the $(eval ) with $(warning ), no errors appear and the target is generated correctly.

If I comment out the code such that just the foreeach function remains, the make succeeds.

make version: 3.80, compiled on Solaris

Suggestions?

Much thanks in advance!

  --Eric

-- 
E r i c   W e s t
address@hidden
Boston, Ma USA