sources in a deep hierarchy, objects flat

[Frink, Alexander]

Hi!

I have my sources in a deep hierarchy and want to compile them into a flat
directory. The module name is unique in the deep hierarchy, so there are no
object name clashes.
Assume I have the following sources

src/some/deep/structure/a/1.c
src/some/deep/structure/a/2.c
src/some/deep/structure/b/3.c

and want the objects to be

obj/flat/1.o
obj/flat/2.o
obj/flat/3.o

and do not want to create and maintain a Makefile in each source subdirectory,
so my only, single Makefile is ./Makefile

I cannot use pattern rules, but I can easily derive the object name from the
source name (replace .c with .o, strip the directory part and add a prefix
obj/flat/). Therefore I tried to use "foreach", "eval" and canned command
sequences to dynamically generate the dependencies and compile steps using
something like the following Makefile

------------ BEGIN MAKEFILE -----------------
SOURCES := $(shell find src -type f -name "*.c")

$(info SOURCES=$(SOURCES))

define compile_rule
SOURCE := $(1)
TARGET := $(addprefix obj/flat/, \
          $(notdir \
          $(patsubst %.c,%.o, \
          $(SOURCE))))
all: $(TARGET)
$(TARGET): $(SOURCE)
        echo compiling $(SOURCE) to $(TARGET)
        touch $(TARGET)
endef

$(info foreach-loop)

$(foreach source,$(SOURCES),$(eval $(call compile_rule,$(source))))
------------ END MAKEFILE -----------------
(In front of the echo and touch lines I use Tabs which get lost due to copy and
paste).

I know that the above Makefile is wrong and I surely need some escaping. In this
form it should be easiest to understand what I wanted to achieve. I tried
various combinations, replacing := by =, using $$ instead of $, but now I think
I got lost with deferred and immediate evaluation, double evaluation by eval
etc.

Using make 3.81, the current result is

SOURCES=src/some/deep/structure/a/1.c src/some/deep/structure/a/2.c
src/some/deep/structure/b/3.c
foreach-loop
echo compiling src/some/deep/structure/a/2.c to obj/flat/1.o
compiling src/some/deep/structure/a/2.c to obj/flat/1.o
touch obj/flat/1.o

Only one file is compiled, and $(SOURCE) and $(TARGET) are out of sync
(2.c/1.o). Running it again gives "Nothing to be done for `all'."

Could anybody please try to explain why and where to escape $ or give a
completely different solution (my other solution would be to write a Perl
script which generates the Makefile, but I prefer to use Make syntax only).

Regards,

Alex
--
Alexander Frink

Debeka Hauptverwaltung
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