Re: Help-make Digest, Vol 77, Issue 5

[xiangfeng shen]

Hi,

 

I have a question about how to replace for loop in clearmake to avoid bad DO.

Makefile:

SUBDIRS = foo bar baz

subdirs:

for dir in $(SUBDIRS); do \

$(MAKE) -C $$dir; \

done

I know We can change above for loop with PHONY target in Gnumake.

But clearmake do not support PHONY target.

 

How to replace for loop in clearmake to avoid bad DO?

Any suggestion?

 

thanks.

carl shen

2009/4/8 <address@hidden>

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Today's Topics:

  1. Re: Simulating multiple wildcards in a match using
     .SECONDEXPANSION? (Michael R. Head)
  2. Add grep command inside makefile. (givemecode)
  3. Re: Simulating multiple wildcards in a match using
     .SECONDEXPANSION? (Danny Boelens)


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Message: 1
Date: Mon, 06 Apr 2009 12:16:56 -0400
From: "Michael R. Head" <address@hidden>
Subject: Re: Simulating multiple wildcards in a match using
       .SECONDEXPANSION?
To: address@hidden
Message-ID: <address@hidden>
Content-Type: text/plain; charset="us-ascii"

On Mon, 2009-04-06 at 14:15 +0200, Danny Boelens wrote:
> Michael R. Head wrote:
> > I'd like to make a rule that generates a output file for each pair in
> > the cross product of two lists of input files. I have a simple makefile
> > that does what I want, but it's ugly.
> >
> > I'm wondering if anyone has any suggestions on improving it. At a
> > minimum, I'd like to get rid of the foreachs in the targets.
>
> You can do that because you know how you constructed the cross product
> targets. In your case: if you replace the underscore ('_') with a space
> (' '), the cross product target falls apart into its components again:

True. But spaces in filenames are evil!

> But looking at your original problem description, I think I'd use
> another approach to solve it. One using a define as 'rule template',
> because it's a bit easier to read and understand in my opinion - but
> that might be just me. Something like this (untested):

Ah! I didn't know about rule templates. That is definitely much nicer,
and something I will have to incorporate into my Make repertoire.

> Hope this helps,
> Danny

thanks,
mike

--
Michael R. Head <address@hidden>
http://www.cs.binghamton.edu/~mike/
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Message: 2
Date: Mon, 6 Apr 2009 08:37:07 -0700 (PDT)
From: givemecode <address@hidden>
Subject: Add grep command inside makefile.
To: address@hidden
Message-ID: <address@hidden>
Content-Type: text/plain; charset=us-ascii


Hello - I have a source tree which has a makefile and subdirectories which
also have a makefile. Each of the subdirectories represents a particular
module of the code. In one of the modules, I want to put a grep command
inside its makefile so when the module is compiled, it searches for
something inside the assembly code that is produced, and fails if it's
found.

I can put the grep command successfully inside the main makefile after all
the compilation is finished and I can make it fail, but how do I move the
grep command into the module's makefile (eg linux.mak) as a tailored flag or
something else?

thank you
--
View this message in context: http://www.nabble.com/Add-grep-command-inside-makefile.-tp22911339p22911339.html
Sent from the Gnu - Make - Help mailing list archive at Nabble.com.





------------------------------

Message: 3
Date: Tue, 07 Apr 2009 09:33:39 +0200
From: Danny Boelens <address@hidden>
Subject: Re: Simulating multiple wildcards in a match using
       .SECONDEXPANSION?
To: address@hidden
Cc: "Michael R. Head" <address@hidden>
Message-ID: <address@hidden>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Michael R. Head wrote:
> On Mon, 2009-04-06 at 14:15 +0200, Danny Boelens wrote:
>> Michael R. Head wrote:
>>> I'm wondering if anyone has any suggestions on improving it. At a
>>> minimum, I'd like to get rid of the foreachs in the targets.
 >>
>> You can do that because you know how you constructed the cross product
>> targets. In your case: if you replace the underscore ('_') with a space
>> (' '), the cross product target falls apart into its components again:
>
> True. But spaces in filenames are evil!

I agree. But I have a feeling you missed my point there. The thing is
that your cross product files still have the underscore ('_') in their
filename, so there won't be any spaces in filenames on disk. But at the
same time the subst call can help in getting a (Makefile internal if you
want) list with the a and b part of the cross product.

So for example you'll still have 'a1_b4' on disk, but 'a1 b4' after the
subst to work with in your Makefile and get the prerequisites without
the foreach stuff.

Bottom line: no evil spaces in filenames!

Anyway, that's all rather irrelevant if you like the other solution :-)

Best regards,
Danny




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