Dependencies of dependencies across make implementations.

[sarah fox]

$ cat Makefile

all: file

file.c: file.h
        @:

file.o: file.c
        cc -o file.o -c file.c

file: file.o
        cc -o file file.o

clean:
        rm -f file.o file

The theory is that editing file.h will cause file.c to be recompiled due to the
dependency chain file.o -> file.c -> file.h.

BSD make appears to get this right:

$ freebsd-make
cc -o file.o -c file.c
cc -o file file.o
$ touch file.h
$ freebsd-make
cc -o file.o -c file.c
cc -o file file.o

As does Solaris, HPUX and IRIX make.

GNU make does not:

$ make
cc -o file.o -c file.c
cc -o file file.o
$ touch file.h
$ make
$

Is there a method to make GNU make behave "correctly" without
introducing GNU make specific syntax?

Sarah