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some questin about Makefile
From: |
loody |
Subject: |
some questin about Makefile |
Date: |
Wed, 16 Sep 2009 21:46:55 +0800 |
Dear all:
below is my makefile.
ifndef TOOLCHAIN
TOOLCHAIN =
endif
#ifeq ($(TOOLCHAIN),sde)
CC = $(TOOLCHAIN)gcc
LD = $(TOOLCHAIN)ld
OBJ2REL = $(TOOLCHAIN)strip --strip-debug
OBJ2BIN = $(TOOLCHAIN)objcopy -O binary
OBJ2SYM = $(TOOLCHAIN)objcopy --only-keep-debug
OBJ2REC = $(TOOLCHAIN)objcopy -O srec
OBJDUMP = $(TOOLCHAIN)objdump -S
OFORMAT = elf32-tradlittlemips
#endif
ROOT = .
SRCDIR = $(ROOT) ./device/display ./device/fatfs ./device/misc
VPATH = ${SRCDIR}
BINDIR = $(ROOT)
INCLUDE =
-I/root/x-tools/mipsel-unknown-linux-uclibc/mipsel-unknown-linux-uclibc/sys-root/usr/include
-I./include -I./device/display -I./device/fatfs -I./device/misc
-I./device/ntstrg -I./device/ntuart -I./device/ntxsub -I./device/VPU
CFLAGS = -g -G0 -mips32r2 -fno-omit-frame-pointer
-fno-optimize-sibling-calls $(INCLUDE)
CFLAGS_A = $(CFLAGS) -D_ASSEMBLER_
OBJ_C = cpufunc.o Interrupt.o main.o memtst.o ntsys.o Display.o
diskio.o FileSystem.o tff.o misc.o
OBJ = cpufunc.o Interrupt.o main.o memtst.o ntsys.o Display.o diskio.o
FileSystem.o tff.o misc.o
.PHONY : all clear depend
all: $(OBJ)
$(OBJ_C) : %.o : %.c
@echo OBJ_C=$(OBJ_C)
@echo prerequisite = $<
@echo target = $@
$(CC) $(CFLAGS) -c $<
clean :
rm -f $(BINDIR)/*.o $(BINDIR)/*.inf $(BINDIR)/depend.mk
depend :
$(CC) $(INCLUDE) -M $(SRC) > depend.mk
-include depend.mk
and my output is
OBJ_C=cpufunc.o Interrupt.o main.o memtst.o ntsys.o Display.o diskio.o
FileSystem.o tff.o misc.o
prerequisite = ./device/fatfs/tff.c
target = tff.o
mipsel-unknown-linux-uclibc-gcc -g -G0 -mips32r2
-fno-omit-frame-pointer -fno-optimize-sibling-calls
-I/root/x-tools/mipsel-unknown-linux-uclibc/mipsel-unknown-linux-uclibc/sys-root/usr/include
-I./include -I./device/display -I./device/fatfs -I./device/misc
-I./device/ntstrg -I./device/ntuart -I./device/ntxsub -I./device/VPU
-c ./device/fatfs/tff.c
my question are:
1. what does the pattern rule of "OBJ_C : %.o : %.c" mean?
2. I purposely assign the member of OBJ_C without directories, but why
the output of $< still has directories?
3. the prerequisite of all is $(OBJ), but why make find $(OBJ_C) as
the prerequisite for execution?
appreciate your help,
miloody
- some questin about Makefile,
loody <=