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Testing the name of a variable passed to a Makefile
From: |
José Luis García Pallero |
Subject: |
Testing the name of a variable passed to a Makefile |
Date: |
Mon, 4 Apr 2011 09:53:06 +0200 |
Hello,
Imagine I pass the name of the compiler when I call make:
make build CC=gcc-4.5
Now, imagine that in my Makefile I have defined that depending on the
compiler I will used different options:
ifeq ($(CC),gcc)
CFLAGS=-Wall -Wextra
endif
ifeq ($(CC),opencc)
CFLAGS=-Wall
endif
But the problen is that gcc, for example, can be called as gcc,
gcc-4.5, gcc-3.3, etc. depending on version and the same for opencc or
another compiler.
So my question is, how can I detect if some string (gcc, for example)
is contained in other string (an input argument, for example)?
Thanks
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José Luis García Pallero
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Use Debian GNU/Linux and enjoy!
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- Testing the name of a variable passed to a Makefile,
José Luis García Pallero <=