Getting the relative pathname of an included makefile

[Mason]

Hello,

I'm trying to write a "robust" build environment using GNU make
and gcc.

For testing purposes, I have the following directory structure:

Makefile
inc
  a.h
  b.h
obj
src
  tata
    x.c
    y.c
    z.c
  toto
    x.c
    y.c
    z.c
  tutu
    x.c
    y.c
    z.c

The idea is that a setenv.sh script will set all the environment
variables necessary to build a specific target, and the object
files will be stored in obj/$(TARGET), mirroring the source tree
structure.

Right now, my Makefile looks like this:

CC = gcc
CFLAGS += -Wall
CFLAGS += -I inc

OBJDIR := obj/$(TARGET)
## explicitly naming source files
SRC := src/tata/x.c src/tata/y.c src/toto/y.c src/tutu/z.c
OBJ := $(SRC:%.c=$(OBJDIR)/%.o)

app: $(OBJ)

$(OBJDIR)/%.o: %.c
        @mkdir -p $(dir $@)
        $(CC) -c $(CFLAGS) -MMD $< -o $@

clean:
        rm -rf $(OBJDIR)

-include $(OBJ:.o=.d)

This works as I intended, with automatic dependency generation,
but I want to "push" the source file listing into each "module"
and include that list from the main makefile.

So I've added a files.mak to every directory in src

For example, src/tata/files.mak contains

SRC += src/tata/x.c src/tata/y.c

And in the main makefile, I do

MODULES := $(wildcard src/*)
SRC :=
-include $(MODULES:%=%/files.mak)
## equivalent to
## -include src/tata/files.mak src/toto/files.mak src/tutu/files.mak

So far, so good.

But I'd like to make files.mak less redundant, by mentioning
only the base filename, e.g.

SRC += x.c y.c

and have a way to have "src/tata/" auto-magically appended.

Something along the lines of

DIR := $(DIRECTORY_OF_THIS_MAKEFILE_RELATIVE_TO_ROOT) # e.g. src/tata
LIST := x.c y.c
SRC += $(LIST:%=$(DIR)/%)

Is there a simple, easy, natural, etc way to do that?
Perhaps some internal MAKE variable, like CURDIR?
(but CURDIR gives the directory of the main Makefile)
Or some shell magic?

-- 
Regards.