Re: Expandable dependencies variables

[Paul Smith]

On Fri, 2012-11-09 at 23:37 +0100, Michael Ludwig wrote:
> Miguel Guedes schrieb am 05.11.2012 um 16:35 (+0000):
> 
> > Is it possible to set dependencies in variables and then have GNU Make
> > expand these dependencies? For instance, let's say we have a project
> > that builds two binaries, foo and bar. Each of foo and bar have their
> > own dependencies as defined below:
> > 
> > 
> > BINARIES := foo bar
> > 
> > FOO_OBJECTS := foo_obj_1 foo_obj_2
> > BAR_OBJECTS := bar_obj_1 bar_obj_2
> > 
> > 
> > Now, how would one setup a generic Makefile such that for each target
> > defined in $(BINARIES) the dependencies $($<_OBJECTS) are added
> > automatically?
> 
> I don't know whether it's possible to solve this using Make - but you
> could possibly use a makro language like m4 or a template and a Perl
> script to achieve what you want.

You can do it easily with GNU make's $(eval ...) function... if you're
willing to restrict your makefiles to use on systems that support it.
However I believe even GNU make 3.81 supported $(eval ...):

        BINARIES := foo bar
        
        foo_OBJECTS := foo_obj_1 foo_obj_2
        bar_OBJECTS := bar_obj_1 bar_obj_2
        
        $(foreach B,$(BINARIES),$(eval $B : $($B_OBJECTS)))

(note not tested).  More complex things can be accomplished by combining
$(eval ...) with $(call ...).

You can also use secondary expansion... but there is a (slight...
probably) performance cost to it.

Or, finally, you can go old-school and use auto-generated included
makefiles, which will work with virtually every version of GNU make out
there:

        BINARIES := foo bar
        
        foo_OBJECTS := foo_obj_1 foo_obj_2
        bar_OBJECTS := bar_obj_1 bar_obj_2
        
        -include generated.mk
        generated.mk: Makefile
                @($(foreach B,$(BINARIES),echo $B: $($B_OBJECTS);):) > $@

Again, untested.