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Re: Problem with makefile
From: |
Hiebert, Darren (IS) |
Subject: |
Re: Problem with makefile |
Date: |
Wed, 6 Mar 2013 20:05:45 +0000 |
Paul,
Attached (and below) is a slight variation of my original makefile that
incorporates your recommendation, but no longer works for any of the
SAMPLE_BINn_OBJECT_FILES (where n is 1, 2, or 3). It replaces the three
different expansions with one foreach.
Darren
--------------------------------------------
define target_assignments
ifneq "$$(strip $$($(1)_$(2)_TARGET))" ""
$(1)_$(2)_OBJECT_FILES := $$(addprefix $$($(1)_DIR),$$($(1)_$(2)_OBJECTS))
endif
endef
define indexed_bin_target
$(call target_assignments,$(1),BIN$(2))
endef
define template
$(1)_TARGET_DIR ?= $$($(1)_DIR)
$(1)_TARGET_NUMBERS ?= 1 2 3
$(foreach index,$$($(1)_TARGET_NUMBERS),$(call
indexed_bin_target,$(1),$(index)))
.PHONY: expansion
expansion:
@ cat Makefile > .tmp.mak
@ echo '$$$$(info $$$$(call template,$(1)))' >> .tmp.mak
@ echo 'nada:' >> .tmp.mak
@ $$(MAKE) -f .tmp.mak nada
@ rm -f .tmp.mak
endef
SAMPLE_DIR = sampledir/
SAMPLE_BIN1_TARGET = sample1
SAMPLE_BIN1_OBJECTS = sample1.o
SAMPLE_BIN2_TARGET = sample2
SAMPLE_BIN2_OBJECTS = sample2.o
SAMPLE_BIN3_TARGET = sample3
SAMPLE_BIN3_OBJECTS = sample3.o
$(eval $(call template,SAMPLE))
.PHONY: print-%
print-%:
@echo $* = $($*)
@echo $* origin is $(origin $*)
--------------------------------------------
-----Original Message-----
From: Paul Smith [mailto:address@hidden
Sent: Wednesday, March 06, 2013 1:18 PM
To: Hiebert, Darren (IS)
Cc: address@hidden
Subject: EXT :Re: Problem with makefile
On Wed, 2013-03-06 at 18:30 +0000, Hiebert, Darren (IS) wrote:
> $(foreach index,$($(1)_TARGET_NUMBERS),$(call
> target_assignments,$(1),BIN$(index)))
This line is quoted incorrectly. You need to write:
$$($(1)_TARGET_NUMBERS)
^^
Otherwise this variable is expanded the first time, when the call is invoked,
before the eval has run, and the value of SAMPLE_TARGET_NUMBERS is not set
until the eval is running so it evaluates to the empty string.
Makefile
Description: Makefile