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From: | Paul Cercueil |
Subject: | Re: [Lightning] jit_qdivr_u trashes JIT_R0 on x86_64 |
Date: | Thu, 22 Aug 2019 22:24:10 +0200 |
Le jeu. 22 août 2019 à 20:39, Paulo =?iso-8859-1?b?Q+lzYXI=?= Pereira de Andrade <address@hidden> a écrit :
Em qua, 21 de ago de 2019 às 10:41, Paul Cercueil <address@hidden> escreveu:Hi,Hi,I noticed that it trashes my JIT_R2 (%r12) register as well... Regards -Paul Le dim. 18 août 2019 à 19:46, Paul Cercueil <address@hidden> a écrit : > Hi Pablo, > > I'm trying to debug an issue I have on my Lightrec project > (https://github.com/pcercuei/lightrec/). > > On x86_64, I'm under the impression that calling jit_qdivr_u() > trashes the JIT_R0 (%eax) register. Looking at the code, it > definitely uses %eax for *something*. Should I expect %eax to be> properly restored after jit_qdivr_u(), or should I avoid using this> register in the first place?As you should be aware, %rax/%rdx must be used for division on x86. Thegenerated code should be generating a spill/reload of %rax and %rdx as appropriate.
I didn't know, now it makes more sense :)
Can you please test with the latest git code? There was a major rewrite ot the code to manage registers live information, what corrected one major known issue, where it did not properly handle a register that was live for a large amount of code, but never referenced in several basic blocks. Usuallya loop. I suspect you might be having the same issue on more complex code generation, and some live state might be missing.
This is with the latest master. Good job on the RISC-V port btw :)
The file check/qalu_div.tst does brute force test of combinations of registers with JIT_R0, JIT_R1, JIT_R2, JIT_V0, JIT_V1, JIT_V2, as well as allocating a temporary register for tests with immediates. But the tests do not properly check for the same register as argument and result for example. But the only invalid case should be the quotient and remainder specified as thesame register.
I call jit_qdiv(reg1, reg2, reg2, reg1)(and also jit_qdiv_u with the same arguments). reg1 and reg2 cannot represent the same register.
Thanks, -Paul
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