Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[goldsimon]

Noam Weissman wrote:
>I am working with STM32F7 with LwIP 2.02 + FreeRTOS 9
>
>D and I cache are enabled.

The drivers supplied by ST, although using DMA transfer, are still copying the 
frame payload to/from pbuf payload using memcpy. If you haven't changed this 
yourself, you have cache line alignment requirements for the driver's tx/93rd 
buffers only, but not for pbufs.

>TX/RX descriptors are hard coded inside DTCM. We have no problems for
>now.

Well, DTCM does not go via the cache, does it? So this is probably unrelated?

>I strongly suggest upgrading to LwIP 2.02 or even 2.03

I always suggest this, too. However, I'm almost sure the OP's issue is not 
solved by simply upgrading.

Simon