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Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/2] target-arm: Add the HSTR_EL2
From: |
Alistair Francis |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/2] target-arm: Add the HSTR_EL2 register |
Date: |
Fri, 13 May 2016 13:39:32 -0700 |
On Fri, May 13, 2016 at 10:46 AM, Peter Maydell
<address@hidden> wrote:
> On 6 May 2016 at 19:11, Alistair Francis <address@hidden> wrote:
>> Add the Hypervisor System Trap Register for EL2.
>>
>> This register is used early in the Linux boot and without it the kernel
>> aborts with a "Synchronous Abort" error.
>>
>> Signed-off-by: Alistair Francis <address@hidden>
>> ---
>>
>> target-arm/helper.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 09638b2..65e8ff1 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -3470,6 +3470,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>> .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
>> .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
>> .type = ARM_CP_CONST, .resetvalue = 0 },
>> + { .name = "HSTR_EL2", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
>> + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>> REGINFO_SENTINEL
>> };
>>
>> @@ -3703,6 +3706,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>> .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
>> .access = PL2_RW,
>> .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
>> + { .name = "HSTR_EL2", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
>> + .access = PL2_RW,
>> + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, },
>> REGINFO_SENTINEL
>> };
>
> Can we have the 32-bit version of the register too, please? (I think
> it should be possible to do this with a STATE_BOTH stanza).
Yep, I think I added it correctly.
>
> Can we have the el2_cp_reginfo implemented to be a reads-as-written
> to a hstr_el2 field in the env->cp15 struct? That way we won't have
> to come back to the regdef struct as and when we actually implement
> the trap bits to do something...
Yep, I have added that as well. Sending V2 now.
Thanks,
Alistair
>
> thanks
> -- PMM
>
- [Qemu-arm] [PATCH v1 0/2] target-arm: Add support for HSTR_EL2, Alistair Francis, 2016/05/06
- [Qemu-arm] [PATCH v1 1/2] target-arm: Add the HSTR_EL2 register, Alistair Francis, 2016/05/06
- [Qemu-arm] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Alistair Francis, 2016/05/06
- Re: [Qemu-arm] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Peter Maydell, 2016/05/06
- Re: [Qemu-arm] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Edgar E. Iglesias, 2016/05/06
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Alistair Francis, 2016/05/09
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Peter Maydell, 2016/05/09
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Alistair Francis, 2016/05/09
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Peter Maydell, 2016/05/10
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Edgar E. Iglesias, 2016/05/10
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Peter Maydell, 2016/05/10
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 2/2] target-arm: Enable EL2 for the A53s and A57s, Alistair Francis, 2016/05/10