[Qemu-arm] [PATCH V2 3/5] target-arm: Add support for PMU register PMXEVCNTR_EL0

[Wei Huang]

To make PMU register support complete, this patch adds support for
PMXEVCNTR_EL0.

Signed-off-by: Wei Huang <address@hidden>
---
 target/arm/helper.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index c8620d9..6b8460a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1255,6 +1255,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
       .accessfn = pmreg_access },
+    { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
+      .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = pmreg_access },
     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
-- 
1.8.3.1