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Re: [Qemu-arm] [Qemu-devel] [PATCH 8/9] target/arm: Support some Thumb i
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH 8/9] target/arm: Support some Thumb insns being always unconditional |
Date: |
Wed, 11 Oct 2017 10:57:42 +0100 |
On 11 October 2017 at 03:52, Richard Henderson
<address@hidden> wrote:
> On 10/09/2017 06:48 AM, Peter Maydell wrote:
>> - if (dc->condexec_mask) {
>> + if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
>> uint32_t cond = dc->condexec_cond;
>>
>> if (cond != 0x0e) { /* Skip conditional when condition is AL. */
>
> Don't you still need to advance the condexec_mask?
Yes -- that happens after we've called disas_thumb{,2}_insn()
in thumb_tr_translate_insn().
This patch just makes always-unconditional insns behave
as if the condition is AL.
thanks
-- PMM
- [Qemu-arm] [PATCH 0/9] v8M: BLXNS, SG, secure function return, Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 7/9] target-arm: Simplify insn_crosses_page(), Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 6/9] target/arm: Pull Thumb insn word loads up to top level, Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 9/9] target/arm: Implement SG instruction corner cases, Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 3/9] target/arm: Implement BLXNS, Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 5/9] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1, Peter Maydell, 2017/10/09