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Re: [Qemu-arm] [Qemu-devel] [PATCH v5 17/31] sdhci: rename the hostctl1
From: |
Alistair Francis |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v5 17/31] sdhci: rename the hostctl1 register |
Date: |
Mon, 8 Jan 2018 13:54:08 -0800 |
On Mon, Jan 8, 2018 at 7:42 AM, Philippe Mathieu-Daudé <address@hidden> wrote:
> As per the Spec v3.00
>
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> include/hw/sd/sdhci.h | 2 +-
> hw/sd/sdhci.c | 14 +++++++-------
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
> index c0098fc920..ecd192ee47 100644
> --- a/include/hw/sd/sdhci.h
> +++ b/include/hw/sd/sdhci.h
> @@ -65,7 +65,7 @@ typedef struct SDHCIState {
> /* Buffer Data Port Register - virtual access point to R and W buffers */
> uint32_t prnsts; /* Present State Register */
> /* 0x28 */
> - uint8_t hostctl; /* Host Control Register */
> + uint8_t hostctl1; /* Host Control Register */
> uint8_t pwrcon; /* Power control Register */
> uint8_t blkgap; /* Block Gap Control Register */
> uint8_t wakcon; /* WakeUp Control Register */
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 3f5e0760f6..d7e247cb48 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -600,7 +600,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr
> *dscr)
> uint32_t adma1 = 0;
> uint64_t adma2 = 0;
> hwaddr entry_addr = (hwaddr)s->admasysaddr;
> - switch (SDHC_DMA_TYPE(s->hostctl)) {
> + switch (SDHC_DMA_TYPE(s->hostctl1)) {
> case SDHC_CTRL_ADMA2_32:
> dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)&adma2,
> sizeof(adma2));
> @@ -789,7 +789,7 @@ static void sdhci_data_transfer(void *opaque)
> SDHCIState *s = (SDHCIState *)opaque;
>
> if (s->trnmod & SDHC_TRNS_DMA) {
> - switch (SDHC_DMA_TYPE(s->hostctl)) {
> + switch (SDHC_DMA_TYPE(s->hostctl1)) {
> case SDHC_CTRL_SDMA:
> if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
> sdhci_sdma_transfer_single_block(s);
> @@ -898,7 +898,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
> unsigned size)
> ret = s->prnsts;
> break;
> case SDHC_HOSTCTL:
> - ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
> + ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
> (s->wakcon << 24);
> break;
> case SDHC_CLKCON:
> @@ -1016,7 +1016,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
> unsigned size)
> MASKED_WRITE(s->sdmasysad, mask, value);
> /* Writing to last byte of sdmasysad might trigger transfer */
> if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) &&
> s->blkcnt &&
> - s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
> + s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
> if (s->trnmod & SDHC_TRNS_MULTI) {
> sdhci_sdma_transfer_multi_blocks(s);
> } else {
> @@ -1068,14 +1068,14 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t
> val, unsigned size)
> if (!(mask & 0xFF0000)) {
> sdhci_blkgap_write(s, value >> 16);
> }
> - MASKED_WRITE(s->hostctl, mask, value);
> + MASKED_WRITE(s->hostctl1, mask, value);
> MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
> MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
> if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5
> ||
> !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
> s->pwrcon &= ~SDHC_POWER_ON;
> }
> - qemu_set_irq(s->access_led, s->hostctl & 1);
> + qemu_set_irq(s->access_led, s->hostctl1 & 1);
> break;
> case SDHC_CLKCON:
> if (!(mask & 0xFF000000)) {
> @@ -1284,7 +1284,7 @@ const VMStateDescription sdhci_vmstate = {
> VMSTATE_UINT16(cmdreg, SDHCIState),
> VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
> VMSTATE_UINT32(prnsts, SDHCIState),
> - VMSTATE_UINT8(hostctl, SDHCIState),
> + VMSTATE_UINT8(hostctl1, SDHCIState),
> VMSTATE_UINT8(pwrcon, SDHCIState),
> VMSTATE_UINT8(blkgap, SDHCIState),
> VMSTATE_UINT8(wakcon, SDHCIState),
> --
> 2.15.1
>
>
- [Qemu-arm] [PATCH v5 10/31] sdhci: add a Designware/Samsung host controller, (continued)
- [Qemu-arm] [PATCH v5 10/31] sdhci: add a Designware/Samsung host controller, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 11/31] hw/arm/exynos4210: use the "samsung, exynos4210-dw-mshc" device, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 12/31] sdhci: add the generic Arasan SDHCI 4.9a PHY controller, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 13/31] hw/arm/xilinx_zynq: use the "arasan, sdhci-4.9a" device, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 14/31] sdhci: add qtest to check the SD Spec version, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 15/31] sdhci: check Spec v2 capabilities qtest, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 16/31] sdhci: add v3 capabilities, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 17/31] sdhci: rename the hostctl1 register, Philippe Mathieu-Daudé, 2018/01/08
- Re: [Qemu-arm] [Qemu-devel] [PATCH v5 17/31] sdhci: rename the hostctl1 register,
Alistair Francis <=
- [Qemu-arm] [PATCH v5 18/31] sdhci: add the Broadcom BCM2835 SDHCI controller, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 19/31] hw/arm/bcm2835_peripherals: use the "brcm, bcm2835-sdhci" device, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 20/31] sdhci: add the Freescale controller for i.MX, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 21/31] hw/arm/fsl-imx6: use the "fsl, imx6q-usdhc" controller, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 22/31] sdhci: add the generic Arasan SDHCI 8.9a PHY, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 23/31] hw/arm/xilinx_zynqmp: use the "arasan, sdhci-8.9a" device, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 24/31] sdhci: let the SYSBUS_SDHCI type be abstract, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 25/31] sdhci: check Spec v3 capabilities qtest, Philippe Mathieu-Daudé, 2018/01/08
- [Qemu-arm] [PATCH v5 26/31] sdhci: remove the deprecated 'capareg' property, Philippe Mathieu-Daudé, 2018/01/08